1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.RobPtr 30import xiangshan.mem.mdp._ 31 32class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 33 34 // params alias 35 private val numRegSrc = backendParams.numRegSrc 36 private val numVecRegSrc = backendParams.numVecRegSrc 37 private val numVecRatPorts = numVecRegSrc + 1 // +1 dst 38 39 println(s"[Rename] numRegSrc: $numRegSrc") 40 41 val io = IO(new Bundle() { 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val robCommits = Input(new RobCommitIO) 44 // from decode 45 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 46 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 47 // ssit read result 48 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 49 // waittable read result 50 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 51 // to rename table 52 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 53 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 54 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 55 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 56 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 57 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 58 // from rename table 59 val int_old_pdest = Vec(CommitWidth, Input(UInt(PhyRegIdxWidth.W))) 60 val fp_old_pdest = Vec(CommitWidth, Input(UInt(PhyRegIdxWidth.W))) 61 val vec_old_pdest = Vec(CommitWidth, Input(UInt(PhyRegIdxWidth.W))) 62 val int_need_free = Vec(CommitWidth, Input(Bool())) 63 // to dispatch1 64 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 65 // for snapshots 66 val snpt = Input(new SnapshotPort) 67 val snptLastEnq = Flipped(ValidIO(new RobPtr)) 68 // debug arch ports 69 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 70 val debug_vconfig_rat = if (backendParams.debugEn) Some(Input(UInt(PhyRegIdxWidth.W))) else None 71 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 72 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 73 // perf only 74 val stallReason = new Bundle { 75 val in = Flipped(new StallReasonIO(RenameWidth)) 76 val out = new StallReasonIO(RenameWidth) 77 } 78 }) 79 80 val compressUnit = Module(new CompressUnit()) 81 // create free list and rat 82 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 83 val fpFreeList = Module(new StdFreeList(VfPhyRegs - FpLogicRegs - VecLogicRegs)) 84 85 intFreeList.io.commit <> io.robCommits 86 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 87 fpFreeList.io.commit <> io.robCommits 88 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 89 90 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 91 // fp and vec share `fpFreeList` 92 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 93 case Reg_I => x.rfWen && x.ldest =/= 0.U 94 case Reg_F => x.fpWen 95 case Reg_V => x.vecWen 96 } 97 def needDestRegCommit[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 98 reg_t match { 99 case Reg_I => x.rfWen 100 case Reg_F => x.fpWen 101 case Reg_V => x.vecWen 102 } 103 } 104 def needDestRegWalk[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 105 reg_t match { 106 case Reg_I => x.rfWen && x.ldest =/= 0.U 107 case Reg_F => x.fpWen 108 case Reg_V => x.vecWen 109 } 110 } 111 112 // connect [redirect + walk] ports for __float point__ & __integer__ free list 113 Seq(fpFreeList, intFreeList).foreach { case fl => 114 fl.io.redirect := io.redirect.valid 115 fl.io.walk := io.robCommits.isWalk 116 } 117 // only when both fp and int free list and dispatch1 has enough space can we do allocation 118 // when isWalk, freelist can definitely allocate 119 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 120 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 121 122 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 123 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 124 125 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 126 sink.valid := source.valid 127 sink.bits := source.bits 128 } 129 val needRobFlags = compressUnit.io.out.needRobFlags 130 val instrSizesVec = compressUnit.io.out.instrSizes 131 val compressMasksVec = compressUnit.io.out.masks 132 133 // speculatively assign the instruction with an robIdx 134 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 135 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 136 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 137 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 138 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 139 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 140 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 141 robIdxHead := robIdxHeadNext 142 143 /** 144 * Rename: allocate free physical register and update rename table 145 */ 146 val uops = Wire(Vec(RenameWidth, new DynInst)) 147 uops.foreach( uop => { 148 uop.srcState := DontCare 149 uop.debugInfo := DontCare 150 uop.lqIdx := DontCare 151 uop.sqIdx := DontCare 152 uop.waitForRobIdx := DontCare 153 uop.singleStep := DontCare 154 uop.snapshot := DontCare 155 uop.dataSource := DontCare 156 uop.l1ExuOH := DontCare 157 }) 158 159 require(RenameWidth >= CommitWidth) 160 val needVecDest = Wire(Vec(RenameWidth, Bool())) 161 val needFpDest = Wire(Vec(RenameWidth, Bool())) 162 val needIntDest = Wire(Vec(RenameWidth, Bool())) 163 val hasValid = Cat(io.in.map(_.valid)).orR 164 private val inHeadValid = io.in.head.valid 165 166 val isMove = Wire(Vec(RenameWidth, Bool())) 167 isMove zip io.in.map(_.bits) foreach { 168 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 169 } 170 171 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 172 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 173 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 174 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 175 176 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 177 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 178 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 179 180 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 181 182 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 183 184 // uop calculation 185 for (i <- 0 until RenameWidth) { 186 for ((name, data) <- uops(i).elements) { 187 if (io.in(i).bits.elements.contains(name)) { 188 data := io.in(i).bits.elements(name) 189 } 190 } 191 192 // update cf according to ssit result 193 uops(i).storeSetHit := io.ssit(i).valid 194 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 195 uops(i).ssid := io.ssit(i).ssid 196 197 // update cf according to waittable result 198 uops(i).loadWaitBit := io.waittable(i) 199 200 uops(i).replayInst := false.B // set by IQ or MemQ 201 // alloc a new phy reg, fp and vec share the `fpFreeList` 202 needVecDest (i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 203 needFpDest (i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 204 needIntDest (i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 205 if (i < CommitWidth) { 206 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_I, io.robCommits.info(i)) 207 walkNeedFpDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_F, io.robCommits.info(i)) 208 walkNeedVecDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_V, io.robCommits.info(i)) 209 walkIsMove(i) := io.robCommits.info(i).isMove 210 } 211 fpFreeList.io.allocateReq(i) := needFpDest(i) || needVecDest(i) 212 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) || walkNeedVecDest(i) 213 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 214 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 215 216 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 217 io.in(i).ready := !hasValid || canOut 218 219 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 220 uops(i).instrSize := instrSizesVec(i) 221 when(isMove(i)) { 222 uops(i).numUops := 0.U 223 uops(i).numWB := 0.U 224 } 225 if (i > 0) { 226 when(!needRobFlags(i - 1)) { 227 uops(i).firstUop := false.B 228 uops(i).ftqPtr := uops(i - 1).ftqPtr 229 uops(i).ftqOffset := uops(i - 1).ftqOffset 230 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 231 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 232 } 233 } 234 when(!needRobFlags(i)) { 235 uops(i).lastUop := false.B 236 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 237 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 238 } 239 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 240 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 241 242 uops(i).psrc(0) := Mux1H(uops(i).srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 243 uops(i).psrc(1) := Mux1H(uops(i).srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 244 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 245 uops(i).psrc(3) := io.vecReadPorts(i)(3) 246 uops(i).psrc(4) := io.vecReadPorts(i)(4) // Todo: vl read port 247 248 // int psrc2 should be bypassed from next instruction if it is fused 249 if (i < RenameWidth - 1) { 250 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 251 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 252 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 253 uops(i).psrc(1) := 0.U 254 } 255 } 256 uops(i).eliminatedMove := isMove(i) 257 258 // update pdest 259 uops(i).pdest := MuxCase(0.U, Seq( 260 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 261 (needFpDest(i) || needVecDest(i)) -> fpFreeList.io.allocatePhyReg(i), 262 )) 263 264 // Assign performance counters 265 uops(i).debugInfo.renameTime := GTimer() 266 267 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 268 io.out(i).bits := uops(i) 269 // Todo: move these shit in decode stage 270 // dirty code for fence. The lsrc is passed by imm. 271 when (io.out(i).bits.fuType === FuType.fence.U) { 272 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 273 } 274 275 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 276// when (io.in(i).bits.isSoftPrefetch) { 277// io.out(i).bits.fuType := FuType.ldu.U 278// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 279// io.out(i).bits.selImm := SelImm.IMM_S 280// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 281// } 282 283 // dirty code for lui+addi(w) fusion 284 if (i < RenameWidth - 1) { 285 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 286 when (fused_lui32) { 287 val lui_imm = io.in(i).bits.imm(19, 0) 288 val add_imm = io.in(i + 1).bits.imm(11, 0) 289 io.out(i).bits.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, add_imm) 290 val lsrcWidth = uops(i).lsrc.head.getWidth 291 val lui_imm_in_imm = ImmUnion.maxLen - Imm_I().len 292 val left_lui_imm = Imm_U().len - lui_imm_in_imm 293 require(2 * lsrcWidth >= left_lui_imm, "cannot fused lui and addi(w) with lsrc") 294 io.out(i).bits.lsrc(0) := lui_imm(lui_imm_in_imm + lsrcWidth - 1, lui_imm_in_imm) 295 io.out(i).bits.lsrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + lsrcWidth) 296 } 297 } 298 299 // write speculative rename table 300 // we update rat later inside commit code 301 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 302 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 303 vecSpecWen(i) := needVecDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 304 305 if (i < CommitWidth) { 306 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 307 walkPdest(i) := io.robCommits.info(i).pdest 308 } else { 309 walkPdest(i) := io.out(i).bits.pdest 310 } 311 } 312 313 /** 314 * How to set psrc: 315 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 316 * - default: psrc from RAT 317 * How to set pdest: 318 * - Mux(isMove, psrc, pdest_from_freelist). 319 * 320 * The critical path of rename lies here: 321 * When move elimination is enabled, we need to update the rat with psrc. 322 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 323 * 324 * If we expand these logic for pdest(N): 325 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 326 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 327 * Mux(bypass(N, N - 2), pdest(N - 2), 328 * ... 329 * Mux(bypass(N, 0), pdest(0), 330 * rat_out(N))...)), 331 * freelist_out(N)) 332 */ 333 // a simple functional model for now 334 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 335 336 // psrc(n) + pdest(1) 337 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 338 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 339 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 340 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 341 for (i <- 1 until RenameWidth) { 342 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 343 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 344 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 345 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 346 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 347 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 348 val indexMatch = in.bits.ldest === t 349 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 350 indexMatch && writeMatch 351 } 352 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 353 } 354 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 355 (z, next) => Mux(next._2, next._1, z) 356 } 357 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 358 (z, next) => Mux(next._2, next._1, z) 359 } 360 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 361 (z, next) => Mux(next._2, next._1, z) 362 } 363 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 364 (z, next) => Mux(next._2, next._1, z) 365 } 366 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 367 (z, next) => Mux(next._2, next._1, z) 368 } 369 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 370 371 // Todo: better implementation for fields reuse 372 // For fused-lui-load, load.src(0) is replaced by the imm. 373 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 374 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 375 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 376 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 377 when (fused_lui_load) { 378 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 379 val lui_imm = io.in(i - 1).bits.imm(19, 0) 380 val ld_imm = io.in(i).bits.imm 381 io.out(i).bits.srcType(0) := SrcType.imm 382 io.out(i).bits.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 383 val psrcWidth = uops(i).psrc.head.getWidth 384 val lui_imm_in_imm = 20/*Todo: uops(i).imm.getWidth*/ - Imm_I().len 385 val left_lui_imm = Imm_U().len - lui_imm_in_imm 386 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 387 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 388 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 389 } 390 391 } 392 393 val genSnapshot = Cat(io.out.map(out => out.fire && out.bits.snapshot)).orR 394 val snapshotCtr = RegInit((4 * CommitWidth).U) 395 val notInSameSnpt = RegNext(distanceBetween(robIdxHeadNext, io.snptLastEnq.bits) >= CommitWidth.U || !io.snptLastEnq.valid) 396 val allowSnpt = if (EnableRenameSnapshot) !snapshotCtr.orR && notInSameSnpt else false.B 397 io.out.zip(io.in).foreach{ case (out, in) => out.bits.snapshot := allowSnpt && (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire } 398 when(genSnapshot) { 399 snapshotCtr := (4 * CommitWidth).U - PopCount(io.out.map(_.fire)) 400 }.elsewhen(io.out.head.fire) { 401 snapshotCtr := Mux(snapshotCtr < PopCount(io.out.map(_.fire)), 0.U, snapshotCtr - PopCount(io.out.map(_.fire))) 402 } 403 404 intFreeList.io.snpt := io.snpt 405 fpFreeList.io.snpt := io.snpt 406 intFreeList.io.snpt.snptEnq := genSnapshot 407 fpFreeList.io.snpt.snptEnq := genSnapshot 408 409 /** 410 * Instructions commit: update freelist and rename table 411 */ 412 for (i <- 0 until CommitWidth) { 413 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 414 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 415 416 // I. RAT Update 417 // When redirect happens (mis-prediction), don't update the rename table 418 io.intRenamePorts(i).wen := intSpecWen(i) 419 io.intRenamePorts(i).addr := uops(i).ldest 420 io.intRenamePorts(i).data := io.out(i).bits.pdest 421 422 io.fpRenamePorts(i).wen := fpSpecWen(i) 423 io.fpRenamePorts(i).addr := uops(i).ldest 424 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 425 426 io.vecRenamePorts(i).wen := vecSpecWen(i) 427 io.vecRenamePorts(i).addr := uops(i).ldest 428 io.vecRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 429 430 // II. Free List Update 431 intFreeList.io.freeReq(i) := io.int_need_free(i) 432 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 433 fpFreeList.io.freeReq(i) := RegNext(commitValid && (needDestRegCommit(Reg_F, io.robCommits.info(i)) || needDestRegCommit(Reg_V, io.robCommits.info(i)))) 434 fpFreeList.io.freePhyReg(i) := Mux(RegNext(needDestRegCommit(Reg_F, io.robCommits.info(i))), io.fp_old_pdest(i), io.vec_old_pdest(i)) 435 } 436 437 /* 438 Debug and performance counters 439 */ 440 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 441 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 442 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 443 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 444 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 445 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 446 ) 447 } 448 449 for ((x,y) <- io.in.zip(io.out)) { 450 printRenameInfo(x, y) 451 } 452 453 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 454 // bad speculation 455 val recStall = io.redirect.valid || io.robCommits.isWalk 456 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.robCommits.isWalk && debugRedirect.debugIsCtrl) 457 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.robCommits.isWalk && debugRedirect.debugIsMemVio) 458 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 459 XSPerfAccumulate("recovery_stall", recStall) 460 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 461 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 462 XSPerfAccumulate("other_recovery_stall", otherRecStall) 463 // freelist stall 464 val notRecStall = !io.out.head.valid && !recStall 465 val intFlStall = notRecStall && inHeadValid && !intFreeList.io.canAllocate 466 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && !fpFreeList.io.canAllocate 467 // other stall 468 val otherStall = notRecStall && !intFlStall && !fpFlStall 469 470 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 471 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 472 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 473 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 474 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 475 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 476 intFlStall -> TopDownCounters.IntFlStall.id.U, 477 fpFlStall -> TopDownCounters.FpFlStall.id.U 478 ) 479 )) 480 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 481 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 482 } 483 484 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 485 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 486 for (i <- 0 until CommitWidth) { 487 val info = io.robCommits.info(i) 488 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 489 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}") 490 } 491 492 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 493 494 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 495 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 496 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 497 XSPerfAccumulate("wait_cycle", !io.in.head.valid && io.out.head.ready) 498 499 // These stall reasons could overlap each other, but we configure the priority as fellows. 500 // walk stall > dispatch stall > int freelist stall > fp freelist stall 501 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 502 private val stallForWalk = inHeadValid && io.robCommits.isWalk 503 private val stallForDispatch = inHeadValid && !io.robCommits.isWalk && !io.out(0).ready 504 private val stallForIntFL = inHeadValid && !io.robCommits.isWalk && io.out(0).ready && !intFreeList.io.canAllocate 505 private val stallForFpFL = inHeadValid && !io.robCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && !fpFreeList.io.canAllocate 506 XSPerfAccumulate("stall_cycle", inHeadStall) 507 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 508 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 509 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 510 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 511 512 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 513 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 514 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 515 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 516 517 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 518 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 519 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 520 521 val renamePerf = Seq( 522 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 523 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 524 ("rename_stall ", inHeadStall), 525 ("rename_stall_cycle_walk ", inHeadValid && io.robCommits.isWalk), 526 ("rename_stall_cycle_dispatch", inHeadValid && !io.robCommits.isWalk && !io.out(0).ready), 527 ("rename_stall_cycle_int ", inHeadValid && !io.robCommits.isWalk && io.out(0).ready && !intFreeList.io.canAllocate), 528 ("rename_stall_cycle_fp ", inHeadValid && !io.robCommits.isWalk && io.out(0).ready && intFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 529 ) 530 val intFlPerf = intFreeList.getPerfEvents 531 val fpFlPerf = fpFreeList.getPerfEvents 532 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 533 generatePerfEvent() 534} 535