1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils._ 7 8class RenameBypassInfo extends XSBundle { 9 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 10 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 11 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 12 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 13} 14 15class Rename extends XSModule { 16 val io = IO(new Bundle() { 17 val redirect = Input(Bool()) 18 val flush = Input(Bool()) 19 val roqCommits = Flipped(new RoqCommitIO) 20 // from decode buffer 21 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 22 // to dispatch1 23 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 24 val renameBypass = Output(new RenameBypassInfo) 25 }) 26 27 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 28 XSInfo( 29 in.valid && in.ready, 30 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 31 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 32 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 33 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 34 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 35 p"old_pdest:${out.bits.old_pdest} " + 36 p"out v:${out.valid} r:${out.ready}\n" 37 ) 38 } 39 40 for((x,y) <- io.in.zip(io.out)){ 41 printRenameInfo(x, y) 42 } 43 44 val intFreeList, fpFreeList = Module(new FreeList).io 45 val intRat = Module(new RenameTable(float = false)).io 46 val fpRat = Module(new RenameTable(float = true)).io 47 val allPhyResource = Seq((intRat, intFreeList, false), (fpRat, fpFreeList, true)) 48 49 allPhyResource.map{ case (rat, freelist, _) => 50 rat.redirect := io.redirect 51 rat.flush := io.flush 52 rat.walkWen := io.roqCommits.isWalk 53 freelist.redirect := io.redirect 54 freelist.flush := io.flush 55 freelist.walk.valid := io.roqCommits.isWalk 56 } 57 58 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 59 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 60 } 61 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 62 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 63 } 64 fpFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(true, i)}) 65 intFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(false, i)}) 66 // walk has higher priority than allocation and thus we don't use isWalk here 67 fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready 68 intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready 69 70 /** 71 * Rename: allocate free physical register and update rename table 72 */ 73 val uops = Wire(Vec(RenameWidth, new MicroOp)) 74 75 uops.foreach( uop => { 76// uop.brMask := DontCare 77// uop.brTag := DontCare 78 uop.src1State := DontCare 79 uop.src2State := DontCare 80 uop.src3State := DontCare 81 uop.roqIdx := DontCare 82 uop.diffTestDebugLrScValid := DontCare 83 uop.debugInfo := DontCare 84 uop.lqIdx := DontCare 85 uop.sqIdx := DontCare 86 }) 87 88 val needFpDest = Wire(Vec(RenameWidth, Bool())) 89 val needIntDest = Wire(Vec(RenameWidth, Bool())) 90 val hasValid = Cat(io.in.map(_.valid)).orR 91 val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk 92 for (i <- 0 until RenameWidth) { 93 uops(i).cf := io.in(i).bits.cf 94 uops(i).ctrl := io.in(i).bits.ctrl 95 uops(i).brTag := io.in(i).bits.brTag 96 97 val inValid = io.in(i).valid 98 99 // alloc a new phy reg 100 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 101 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 102 fpFreeList.req.allocReqs(i) := needFpDest(i) 103 intFreeList.req.allocReqs(i) := needIntDest(i) 104 105 io.in(i).ready := !hasValid || canOut 106 107 // do checkpoints when a branch inst come 108 // for(fl <- Seq(fpFreeList, intFreeList)){ 109 // fl.cpReqs(i).valid := inValid 110 // fl.cpReqs(i).bits := io.in(i).bits.brTag 111 // } 112 113 uops(i).pdest := Mux(needIntDest(i), 114 intFreeList.req.pdests(i), 115 Mux( 116 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 117 0.U, fpFreeList.req.pdests(i) 118 ) 119 ) 120 121 io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk 122 io.out(i).bits := uops(i) 123 124 // write speculative rename table 125 allPhyResource.map{ case (rat, freelist, _) => 126 val specWen = freelist.req.allocReqs(i) && freelist.req.canAlloc && freelist.req.doAlloc && !io.roqCommits.isWalk 127 128 rat.specWritePorts(i).wen := specWen 129 rat.specWritePorts(i).addr := uops(i).ctrl.ldest 130 rat.specWritePorts(i).wdata := freelist.req.pdests(i) 131 132 freelist.deallocReqs(i) := specWen 133 } 134 135 // read rename table 136 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 137 val rat = if(fp) fpRat else intRat 138 val srcCnt = lsrcList.size 139 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 140 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 141 for(k <- 0 until srcCnt+1){ 142 val rportIdx = i * (srcCnt+1) + k 143 if(k != srcCnt){ 144 rat.readPorts(rportIdx).addr := lsrcList(k) 145 psrcVec(k) := rat.readPorts(rportIdx).rdata 146 } else { 147 rat.readPorts(rportIdx).addr := ldest 148 old_pdest := rat.readPorts(rportIdx).rdata 149 } 150 } 151 (psrcVec, old_pdest) 152 } 153 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 154 val ldest = uops(i).ctrl.ldest 155 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 156 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 157 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 158 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 159 uops(i).psrc3 := fpPhySrcVec(2) 160 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 161 } 162 163 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 164 // Instead, we determine whether there're some dependences between the valid instructions. 165 for (i <- 1 until RenameWidth) { 166 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 167 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp 168 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg 169 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1 170 }).reverse) 171 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 172 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp 173 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg 174 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2 175 }).reverse) 176 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 177 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp 178 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg 179 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3 180 }).reverse) 181 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 182 val fpMatch = needFpDest(j) && needFpDest(i) 183 val intMatch = needIntDest(j) && needIntDest(i) 184 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 185 }).reverse) 186 } 187 188 /** 189 * Instructions commit: update freelist and rename table 190 */ 191 for (i <- 0 until CommitWidth) { 192 if (i >= RenameWidth) { 193 allPhyResource.map{ case (rat, _, _) => 194 rat.specWritePorts(i).wen := false.B 195 rat.specWritePorts(i).addr := DontCare 196 rat.specWritePorts(i).wdata := DontCare 197 } 198 } 199 200 allPhyResource.map{ case (rat, freelist, fp) => 201 // walk back write 202 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 203 204 when (commitDestValid && io.roqCommits.isWalk) { 205 rat.specWritePorts(i).wen := true.B 206 rat.specWritePorts(i).addr := io.roqCommits.info(i).ldest 207 rat.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 208 XSInfo({if(fp) p"fp" else p"int "} + p"walk: " + 209 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n") 210 } 211 212 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 213 rat.archWritePorts(i).addr := io.roqCommits.info(i).ldest 214 rat.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 215 216 XSInfo(rat.archWritePorts(i).wen, 217 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 218 p" pdest:${rat.archWritePorts(i).wdata}\n" 219 ) 220 221 freelist.deallocReqs(i) := rat.archWritePorts(i).wen 222 freelist.deallocPregs(i) := io.roqCommits.info(i).old_pdest 223 } 224 } 225} 226