1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.{RobEnqIO, RobPtr} 30import xiangshan.mem.mdp._ 31import xiangshan.ExceptionNO._ 32import xiangshan.backend.fu.FuType._ 33import xiangshan.mem.{EewLog2, GenUSWholeEmul} 34import xiangshan.mem.GenRealFlowNum 35import xiangshan.backend.trace._ 36import xiangshan.backend.decode.isa.bitfield.{OPCODE5Bit, XSInstBitFields} 37import xiangshan.backend.fu.util.CSRConst 38 39class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 40 41 // params alias 42 private val numRegSrc = backendParams.numRegSrc 43 private val numVecRegSrc = backendParams.numVecRegSrc 44 private val numVecRatPorts = numVecRegSrc 45 46 println(s"[Rename] numRegSrc: $numRegSrc") 47 48 val io = IO(new Bundle() { 49 val redirect = Flipped(ValidIO(new Redirect)) 50 val rabCommits = Input(new RabCommitIO) 51 // from csr 52 val singleStep = Input(Bool()) 53 // from decode 54 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 55 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 56 // ssit read result 57 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 58 // waittable read result 59 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 60 // to rename table 61 val intReadPorts = Vec(RenameWidth, Vec(2, Input(UInt(PhyRegIdxWidth.W)))) 62 val fpReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 63 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 64 val v0ReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 65 val vlReadPorts = Vec(RenameWidth, Vec(1, Input(UInt(PhyRegIdxWidth.W)))) 66 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(IntLogicRegs)))) 67 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(FpLogicRegs)))) 68 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(VecLogicRegs)))) 69 val v0RenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(V0LogicRegs)))) 70 val vlRenamePorts = Vec(RenameWidth, Output(new RatWritePort(log2Ceil(VlLogicRegs)))) 71 // from rename table 72 val int_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 73 val fp_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 74 val vec_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 75 val v0_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 76 val vl_old_pdest = Vec(RabCommitWidth, Input(UInt(PhyRegIdxWidth.W))) 77 val int_need_free = Vec(RabCommitWidth, Input(Bool())) 78 // to dispatch1 79 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 80 // for snapshots 81 val snpt = Input(new SnapshotPort) 82 val snptLastEnq = Flipped(ValidIO(new RobPtr)) 83 val snptIsFull= Input(Bool()) 84 // debug arch ports 85 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 86 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Input(UInt(PhyRegIdxWidth.W)))) else None 87 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Input(UInt(PhyRegIdxWidth.W)))) else None 88 val debug_v0_rat = if (backendParams.debugEn) Some(Vec(1, Input(UInt(PhyRegIdxWidth.W)))) else None 89 val debug_vl_rat = if (backendParams.debugEn) Some(Vec(1, Input(UInt(PhyRegIdxWidth.W)))) else None 90 // perf only 91 val stallReason = new Bundle { 92 val in = Flipped(new StallReasonIO(RenameWidth)) 93 val out = new StallReasonIO(RenameWidth) 94 } 95 }) 96 97 // io alias 98 private val dispatchCanAcc = io.out.head.ready 99 100 val compressUnit = Module(new CompressUnit()) 101 // create free list and rat 102 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 103 val fpFreeList = Module(new StdFreeList(FpPhyRegs - FpLogicRegs, FpLogicRegs, Reg_F)) 104 val vecFreeList = Module(new StdFreeList(VfPhyRegs - VecLogicRegs, VecLogicRegs, Reg_V, 31)) 105 val v0FreeList = Module(new StdFreeList(V0PhyRegs - V0LogicRegs, V0LogicRegs, Reg_V0, 1)) 106 val vlFreeList = Module(new StdFreeList(VlPhyRegs - VlLogicRegs, VlLogicRegs, Reg_Vl, 1)) 107 108 109 intFreeList.io.commit <> io.rabCommits 110 intFreeList.io.debug_rat.foreach(_ <> io.debug_int_rat.get) 111 fpFreeList.io.commit <> io.rabCommits 112 fpFreeList.io.debug_rat.foreach(_ <> io.debug_fp_rat.get) 113 vecFreeList.io.commit <> io.rabCommits 114 vecFreeList.io.debug_rat.foreach(_ <> io.debug_vec_rat.get) 115 v0FreeList.io.commit <> io.rabCommits 116 v0FreeList.io.debug_rat.foreach(_ <> io.debug_v0_rat.get) 117 vlFreeList.io.commit <> io.rabCommits 118 vlFreeList.io.debug_rat.foreach(_ <> io.debug_vl_rat.get) 119 120 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 121 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 122 case Reg_I => x.rfWen 123 case Reg_F => x.fpWen 124 case Reg_V => x.vecWen 125 case Reg_V0 => x.v0Wen 126 case Reg_Vl => x.vlWen 127 } 128 def needDestRegCommit[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 129 reg_t match { 130 case Reg_I => x.rfWen 131 case Reg_F => x.fpWen 132 case Reg_V => x.vecWen 133 case Reg_V0 => x.v0Wen 134 case Reg_Vl => x.vlWen 135 } 136 } 137 def needDestRegWalk[T <: RabCommitInfo](reg_t: RegType, x: T): Bool = { 138 reg_t match { 139 case Reg_I => x.rfWen 140 case Reg_F => x.fpWen 141 case Reg_V => x.vecWen 142 case Reg_V0 => x.v0Wen 143 case Reg_Vl => x.vlWen 144 } 145 } 146 147 // connect [redirect + walk] ports for fp & vec & int free list 148 Seq(fpFreeList, vecFreeList, intFreeList, v0FreeList, vlFreeList).foreach { case fl => 149 fl.io.redirect := io.redirect.valid 150 fl.io.walk := io.rabCommits.isWalk 151 } 152 // only when all free list and dispatch1 has enough space can we do allocation 153 // when isWalk, freelist can definitely allocate 154 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 155 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 156 vecFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 157 v0FreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 158 vlFreeList.io.doAllocate := intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && dispatchCanAcc || io.rabCommits.isWalk 159 160 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ vec free list ready ++ not walk 161 val canOut = dispatchCanAcc && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 162 163 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 164 sink.valid := source.valid && !io.singleStep 165 sink.bits := source.bits 166 } 167 val needRobFlags = compressUnit.io.out.needRobFlags 168 val instrSizesVec = compressUnit.io.out.instrSizes 169 val compressMasksVec = compressUnit.io.out.masks 170 171 // speculatively assign the instruction with an robIdx 172 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 173 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 174 val lastCycleMisprediction = GatedValidRegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 175 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 176 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 177 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 178 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 179 robIdxHead := robIdxHeadNext 180 181 /** 182 * Rename: allocate free physical register and update rename table 183 */ 184 val uops = Wire(Vec(RenameWidth, new DynInst)) 185 uops.foreach( uop => { 186 uop.srcState := DontCare 187 uop.debugInfo := DontCare 188 uop.lqIdx := DontCare 189 uop.sqIdx := DontCare 190 uop.waitForRobIdx := DontCare 191 uop.singleStep := DontCare 192 uop.snapshot := DontCare 193 uop.srcLoadDependency := DontCare 194 uop.numLsElem := DontCare 195 uop.hasException := DontCare 196 uop.useRegCache := DontCare 197 uop.regCacheIdx := DontCare 198 uop.traceBlockInPipe := DontCare 199 }) 200 private val inst = Wire(Vec(RenameWidth, new XSInstBitFields)) 201 private val isCsr = Wire(Vec(RenameWidth, Bool())) 202 private val isCsrr = Wire(Vec(RenameWidth, Bool())) 203 private val isRoCsrr = Wire(Vec(RenameWidth, Bool())) 204 private val fuType = uops.map(_.fuType) 205 private val fuOpType = uops.map(_.fuOpType) 206 private val vtype = uops.map(_.vpu.vtype) 207 private val sew = vtype.map(_.vsew) 208 private val lmul = vtype.map(_.vlmul) 209 private val eew = uops.map(_.vpu.veew) 210 private val mop = fuOpType.map(fuOpTypeItem => LSUOpType.getVecLSMop(fuOpTypeItem)) 211 private val isVlsType = fuType.map(fuTypeItem => isVls(fuTypeItem)) 212 private val isSegment = fuType.map(fuTypeItem => isVsegls(fuTypeItem)) 213 private val isUnitStride = fuOpType.map(fuOpTypeItem => LSUOpType.isAllUS(fuOpTypeItem)) 214 private val nf = fuOpType.zip(uops.map(_.vpu.nf)).map { case (fuOpTypeItem, nfItem) => Mux(LSUOpType.isWhole(fuOpTypeItem), 0.U, nfItem) } 215 private val mulBits = 3 // dirty code 216 private val emul = fuOpType.zipWithIndex.map { case (fuOpTypeItem, index) => 217 Mux( 218 LSUOpType.isWhole(fuOpTypeItem), 219 GenUSWholeEmul(nf(index)), 220 Mux( 221 LSUOpType.isMasked(fuOpTypeItem), 222 0.U(mulBits.W), 223 EewLog2(eew(index)) - sew(index) + lmul(index) 224 ) 225 ) 226 } 227 private val isVecUnitType = isVlsType.zip(isUnitStride).map { case (isVlsTypeItme, isUnitStrideItem) => 228 isVlsTypeItme && isUnitStrideItem 229 } 230 private val instType = isSegment.zip(mop).map { case (isSegementItem, mopItem) => Cat(isSegementItem, mopItem) } 231 // There is no way to calculate the 'flow' for 'unit-stride' exactly: 232 // Whether 'unit-stride' needs to be split can only be known after obtaining the address. 233 // For scalar instructions, this is not handled here, and different assignments are done later according to the situation. 234 private val numLsElem = instType.zipWithIndex.map { case (instTypeItem, index) => 235 Mux( 236 isVecUnitType(index), 237 VecMemUnitStrideMaxFlowNum.U, 238 GenRealFlowNum(instTypeItem, emul(index), lmul(index), eew(index), sew(index)) 239 ) 240 } 241 uops.zipWithIndex.map { case(u, i) => 242 u.numLsElem := Mux(io.in(i).valid & isVlsType(i), numLsElem(i), 0.U) 243 } 244 245 val needVecDest = Wire(Vec(RenameWidth, Bool())) 246 val needFpDest = Wire(Vec(RenameWidth, Bool())) 247 val needIntDest = Wire(Vec(RenameWidth, Bool())) 248 val needV0Dest = Wire(Vec(RenameWidth, Bool())) 249 val needVlDest = Wire(Vec(RenameWidth, Bool())) 250 private val inHeadValid = io.in.head.valid 251 252 val isMove = Wire(Vec(RenameWidth, Bool())) 253 isMove zip io.in.map(_.bits) foreach { 254 case (move, in) => move := Mux(in.exceptionVec.asUInt.orR, false.B, in.isMove) 255 } 256 257 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 258 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 259 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 260 val walkNeedV0Dest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 261 val walkNeedVlDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 262 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 263 264 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 265 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 266 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 267 val v0SpecWen = Wire(Vec(RenameWidth, Bool())) 268 val vlSpecWen = Wire(Vec(RenameWidth, Bool())) 269 270 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 271 272 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 273 274 // uop calculation 275 for (i <- 0 until RenameWidth) { 276 (uops(i): Data).waiveAll :<= (io.in(i).bits: Data).waiveAll 277 278 // read only CSRR instruction support: remove blockBackward and waitForward 279 inst(i) := uops(i).instr.asTypeOf(new XSInstBitFields) 280 isCsr(i) := inst(i).OPCODE5Bit === OPCODE5Bit.SYSTEM && inst(i).FUNCT3(1, 0) =/= 0.U 281 isCsrr(i) := isCsr(i) && inst(i).FUNCT3 === BitPat("b?1?") && inst(i).RS1 === 0.U 282 isRoCsrr(i) := isCsrr(i) && LookupTreeDefault( 283 inst(i).CSRIDX, false.B, CSRConst.roCsrrAddr.map(_.U -> true.B)) 284 285 /* 286 * For read-only CSRs, CSRR instructions do not need to wait forward instructions to finish. 287 * For all CSRs, CSRR instructions do not need to block backward instructions for issuing. 288 * Signal "isCsrr" contains not only alias instruction CSRR, but also other csr instructions which 289 * do not require write to any CSR. 290 */ 291 uops(i).waitForward := io.in(i).bits.waitForward && !isRoCsrr(i) 292 uops(i).blockBackward := io.in(i).bits.blockBackward && !isCsrr(i) 293 294 // update cf according to ssit result 295 uops(i).storeSetHit := io.ssit(i).valid 296 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 297 uops(i).ssid := io.ssit(i).ssid 298 299 // update cf according to waittable result 300 uops(i).loadWaitBit := io.waittable(i) 301 302 uops(i).replayInst := false.B // set by IQ or MemQ 303 // alloc a new phy reg 304 needV0Dest(i) := io.in(i).valid && needDestReg(Reg_V0, io.in(i).bits) 305 needVlDest(i) := io.in(i).valid && needDestReg(Reg_Vl, io.in(i).bits) 306 needVecDest(i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 307 needFpDest(i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 308 needIntDest(i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 309 if (i < RabCommitWidth) { 310 walkNeedIntDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_I, io.rabCommits.info(i)) 311 walkNeedFpDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_F, io.rabCommits.info(i)) 312 walkNeedVecDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V, io.rabCommits.info(i)) 313 walkNeedV0Dest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_V0, io.rabCommits.info(i)) 314 walkNeedVlDest(i) := io.rabCommits.walkValid(i) && needDestRegWalk(Reg_Vl, io.rabCommits.info(i)) 315 walkIsMove(i) := io.rabCommits.info(i).isMove 316 } 317 fpFreeList.io.allocateReq(i) := needFpDest(i) 318 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) 319 vecFreeList.io.allocateReq(i) := needVecDest(i) 320 vecFreeList.io.walkReq(i) := walkNeedVecDest(i) 321 v0FreeList.io.allocateReq(i) := needV0Dest(i) 322 v0FreeList.io.walkReq(i) := walkNeedV0Dest(i) 323 vlFreeList.io.allocateReq(i) := needVlDest(i) 324 vlFreeList.io.walkReq(i) := walkNeedVlDest(i) 325 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 326 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 327 328 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 329 io.in(i).ready := !io.in(0).valid || canOut 330 331 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 332 uops(i).instrSize := instrSizesVec(i) 333 val hasExceptionExceptFlushPipe = Cat(selectFrontend(uops(i).exceptionVec) :+ uops(i).exceptionVec(illegalInstr) :+ uops(i).exceptionVec(virtualInstr)).orR || TriggerAction.isDmode(uops(i).trigger) 334 when(isMove(i) || hasExceptionExceptFlushPipe) { 335 uops(i).numUops := 0.U 336 uops(i).numWB := 0.U 337 } 338 if (i > 0) { 339 when(!needRobFlags(i - 1)) { 340 uops(i).firstUop := false.B 341 uops(i).ftqPtr := uops(i - 1).ftqPtr 342 uops(i).ftqOffset := uops(i - 1).ftqOffset 343 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 344 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 345 } 346 } 347 when(!needRobFlags(i)) { 348 uops(i).lastUop := false.B 349 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 350 uops(i).numWB := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 351 } 352 uops(i).wfflags := (compressMasksVec(i) & Cat(io.in.map(_.bits.wfflags).reverse)).orR 353 uops(i).dirtyFs := (compressMasksVec(i) & Cat(io.in.map(_.bits.fpWen).reverse)).orR 354 // vector instructions' uopSplitType cannot be UopSplitType.SCA_SIM 355 uops(i).dirtyVs := (compressMasksVec(i) & Cat(io.in.map(_.bits.uopSplitType =/= UopSplitType.SCA_SIM).reverse)).orR 356 // psrc0,psrc1,psrc2 don't require v0ReadPorts because their srcType can distinguish whether they are V0 or not 357 uops(i).psrc(0) := Mux1H(uops(i).srcType(0)(2, 0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 358 uops(i).psrc(1) := Mux1H(uops(i).srcType(1)(2, 0), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 359 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 360 uops(i).psrc(3) := io.v0ReadPorts(i)(0) 361 uops(i).psrc(4) := io.vlReadPorts(i)(0) 362 363 // int psrc2 should be bypassed from next instruction if it is fused 364 if (i < RenameWidth - 1) { 365 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 366 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 367 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 368 uops(i).psrc(1) := 0.U 369 } 370 } 371 uops(i).eliminatedMove := isMove(i) 372 373 // update pdest 374 uops(i).pdest := MuxCase(0.U, Seq( 375 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 376 needFpDest(i) -> fpFreeList.io.allocatePhyReg(i), 377 needVecDest(i) -> vecFreeList.io.allocatePhyReg(i), 378 needV0Dest(i) -> v0FreeList.io.allocatePhyReg(i), 379 needVlDest(i) -> vlFreeList.io.allocatePhyReg(i), 380 )) 381 382 // Assign performance counters 383 uops(i).debugInfo.renameTime := GTimer() 384 385 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !io.rabCommits.isWalk 386 io.out(i).bits := uops(i) 387 // Todo: move these shit in decode stage 388 // dirty code for fence. The lsrc is passed by imm. 389 when (io.out(i).bits.fuType === FuType.fence.U) { 390 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 391 } 392 393 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 394// when (io.in(i).bits.isSoftPrefetch) { 395// io.out(i).bits.fuType := FuType.ldu.U 396// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 397// io.out(i).bits.selImm := SelImm.IMM_S 398// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 399// } 400 401 // dirty code for lui+addi(w) fusion 402 if (i < RenameWidth - 1) { 403 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 404 when (fused_lui32) { 405 val lui_imm = io.in(i).bits.imm(19, 0) 406 val add_imm = io.in(i + 1).bits.imm(11, 0) 407 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + add_imm.getWidth) 408 io.out(i).bits.imm := Cat(lui_imm, add_imm) 409 } 410 } 411 412 // write speculative rename table 413 // we update rat later inside commit code 414 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 415 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 416 vecSpecWen(i) := needVecDest(i) && vecFreeList.io.canAllocate && vecFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 417 v0SpecWen(i) := needV0Dest(i) && v0FreeList.io.canAllocate && v0FreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 418 vlSpecWen(i) := needVlDest(i) && vlFreeList.io.canAllocate && vlFreeList.io.doAllocate && !io.rabCommits.isWalk && !io.redirect.valid 419 420 421 if (i < RabCommitWidth) { 422 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 423 walkPdest(i) := io.rabCommits.info(i).pdest 424 } else { 425 walkPdest(i) := io.out(i).bits.pdest 426 } 427 } 428 429 /** 430 * trace begin 431 */ 432 val inVec = io.in.map(_.bits) 433 val canRobCompressVec = inVec.map(_.canRobCompress) 434 val isRVCVec = inVec.map(_.preDecodeInfo.isRVC) 435 val halfWordNumVec = (0 until RenameWidth).map{ 436 i => compressMasksVec(i).asBools.zip(isRVCVec).map{ 437 case (mask, isRVC) => Mux(mask, Mux(isRVC, 1.U, 2.U), 0.U) 438 } 439 } 440 441 for (i <- 0 until RenameWidth) { 442 // iretire 443 uops(i).traceBlockInPipe.iretire := Mux(canRobCompressVec(i), 444 halfWordNumVec(i).reduce(_ +& _), 445 Mux(isRVCVec(i), 1.U, 2.U) 446 ) 447 448 // ilastsize 449 val j = i 450 val lastIsRVC = WireInit(false.B) 451 (j until RenameWidth).map { j => 452 when(compressMasksVec(i)(j)) { 453 lastIsRVC := io.in(j).bits.preDecodeInfo.isRVC 454 } 455 } 456 457 uops(i).traceBlockInPipe.ilastsize := Mux(canRobCompressVec(i), 458 Mux(lastIsRVC, Ilastsize.HalfWord, Ilastsize.Word), 459 Mux(isRVCVec(i), Ilastsize.HalfWord, Ilastsize.Word) 460 ) 461 462 // itype 463 uops(i).traceBlockInPipe.itype := Itype.jumpTypeGen(inVec(i).preDecodeInfo.brType, inVec(i).ldest.asTypeOf(new OpRegType), inVec(i).lsrc(0).asTypeOf((new OpRegType))) 464 } 465 /** 466 * trace end 467 */ 468 469 /** 470 * How to set psrc: 471 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 472 * - default: psrc from RAT 473 * How to set pdest: 474 * - Mux(isMove, psrc, pdest_from_freelist). 475 * 476 * The critical path of rename lies here: 477 * When move elimination is enabled, we need to update the rat with psrc. 478 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 479 * 480 * If we expand these logic for pdest(N): 481 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 482 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 483 * Mux(bypass(N, N - 2), pdest(N - 2), 484 * ... 485 * Mux(bypass(N, 0), pdest(0), 486 * rat_out(N))...)), 487 * freelist_out(N)) 488 */ 489 // a simple functional model for now 490 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 491 492 // psrc(n) + pdest(1) 493 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 494 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 495 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 496 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 497 for (i <- 1 until RenameWidth) { 498 val v0Cond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 499 if (i == 3) (s === SrcType.vp) || (s === SrcType.v0) 500 else false.B 501 } :+ needV0Dest(i) 502 val vlCond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) => 503 if (i == 4) s === SrcType.vp 504 else false.B 505 } :+ needVlDest(i) 506 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 507 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 508 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 509 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 510 for ((((((cond1, (condV0, condVl)), cond2), cond3), t), j) <- vecCond.zip(v0Cond.zip(vlCond)).zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 511 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 512 val indexMatch = in.bits.ldest === t 513 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 514 val v0vlMatch = condV0 && needV0Dest(j) || condVl && needVlDest(j) 515 indexMatch && writeMatch || v0vlMatch 516 } 517 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 518 } 519 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 520 (z, next) => Mux(next._2, next._1, z) 521 } 522 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 523 (z, next) => Mux(next._2, next._1, z) 524 } 525 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 526 (z, next) => Mux(next._2, next._1, z) 527 } 528 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 529 (z, next) => Mux(next._2, next._1, z) 530 } 531 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 532 (z, next) => Mux(next._2, next._1, z) 533 } 534 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 535 536 // Todo: better implementation for fields reuse 537 // For fused-lui-load, load.src(0) is replaced by the imm. 538 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 539 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 540 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 541 val fused_lui_load = last_is_lui && this_is_load && lui_to_load 542 when (fused_lui_load) { 543 // The first LOAD operand (base address) is replaced by LUI-imm and stored in imm 544 val lui_imm = io.in(i - 1).bits.imm(ImmUnion.U.len - 1, 0) 545 val ld_imm = io.in(i).bits.imm(ImmUnion.I.len - 1, 0) 546 require(io.out(i).bits.imm.getWidth >= lui_imm.getWidth + ld_imm.getWidth) 547 io.out(i).bits.srcType(0) := SrcType.imm 548 io.out(i).bits.imm := Cat(lui_imm, ld_imm) 549 } 550 551 } 552 553 val genSnapshot = Cat(io.out.map(out => out.fire && out.bits.snapshot)).orR 554 val lastCycleCreateSnpt = RegInit(false.B) 555 lastCycleCreateSnpt := genSnapshot && !io.snptIsFull 556 val sameSnptDistance = (RobCommitWidth * 4).U 557 // notInSameSnpt: 1.robidxHead - snapLastEnq >= sameSnptDistance 2.no snap 558 val notInSameSnpt = GatedValidRegNext(distanceBetween(robIdxHeadNext, io.snptLastEnq.bits) >= sameSnptDistance || !io.snptLastEnq.valid) 559 val allowSnpt = if (EnableRenameSnapshot) notInSameSnpt && !lastCycleCreateSnpt && io.in.head.bits.firstUop else false.B 560 io.out.zip(io.in).foreach{ case (out, in) => out.bits.snapshot := allowSnpt && (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire } 561 io.out.map{ x => 562 x.bits.hasException := Cat(selectFrontend(x.bits.exceptionVec) :+ x.bits.exceptionVec(illegalInstr) :+ x.bits.exceptionVec(virtualInstr)).orR || TriggerAction.isDmode(x.bits.trigger) 563 } 564 if(backendParams.debugEn){ 565 dontTouch(robIdxHeadNext) 566 dontTouch(notInSameSnpt) 567 dontTouch(genSnapshot) 568 } 569 intFreeList.io.snpt := io.snpt 570 fpFreeList.io.snpt := io.snpt 571 vecFreeList.io.snpt := io.snpt 572 v0FreeList.io.snpt := io.snpt 573 vlFreeList.io.snpt := io.snpt 574 intFreeList.io.snpt.snptEnq := genSnapshot 575 fpFreeList.io.snpt.snptEnq := genSnapshot 576 vecFreeList.io.snpt.snptEnq := genSnapshot 577 v0FreeList.io.snpt.snptEnq := genSnapshot 578 vlFreeList.io.snpt.snptEnq := genSnapshot 579 580 /** 581 * Instructions commit: update freelist and rename table 582 */ 583 for (i <- 0 until RabCommitWidth) { 584 val commitValid = io.rabCommits.isCommit && io.rabCommits.commitValid(i) 585 val walkValid = io.rabCommits.isWalk && io.rabCommits.walkValid(i) 586 587 // I. RAT Update 588 // When redirect happens (mis-prediction), don't update the rename table 589 io.intRenamePorts(i).wen := intSpecWen(i) 590 io.intRenamePorts(i).addr := uops(i).ldest(log2Ceil(IntLogicRegs) - 1, 0) 591 io.intRenamePorts(i).data := io.out(i).bits.pdest 592 593 io.fpRenamePorts(i).wen := fpSpecWen(i) 594 io.fpRenamePorts(i).addr := uops(i).ldest(log2Ceil(FpLogicRegs) - 1, 0) 595 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 596 597 io.vecRenamePorts(i).wen := vecSpecWen(i) 598 io.vecRenamePorts(i).addr := uops(i).ldest(log2Ceil(VecLogicRegs) - 1, 0) 599 io.vecRenamePorts(i).data := vecFreeList.io.allocatePhyReg(i) 600 601 io.v0RenamePorts(i).wen := v0SpecWen(i) 602 io.v0RenamePorts(i).addr := uops(i).ldest(log2Ceil(V0LogicRegs) - 1, 0) 603 io.v0RenamePorts(i).data := v0FreeList.io.allocatePhyReg(i) 604 605 io.vlRenamePorts(i).wen := vlSpecWen(i) 606 io.vlRenamePorts(i).addr := uops(i).ldest(log2Ceil(VlLogicRegs) - 1, 0) 607 io.vlRenamePorts(i).data := vlFreeList.io.allocatePhyReg(i) 608 609 // II. Free List Update 610 intFreeList.io.freeReq(i) := io.int_need_free(i) 611 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 612 fpFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_F, io.rabCommits.info(i))) 613 fpFreeList.io.freePhyReg(i) := io.fp_old_pdest(i) 614 vecFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V, io.rabCommits.info(i))) 615 vecFreeList.io.freePhyReg(i) := io.vec_old_pdest(i) 616 v0FreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_V0, io.rabCommits.info(i))) 617 v0FreeList.io.freePhyReg(i) := io.v0_old_pdest(i) 618 vlFreeList.io.freeReq(i) := GatedValidRegNext(commitValid && needDestRegCommit(Reg_Vl, io.rabCommits.info(i))) 619 vlFreeList.io.freePhyReg(i) := io.vl_old_pdest(i) 620 } 621 622 /* 623 Debug and performance counters 624 */ 625 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 626 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 627 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 628 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 629 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 630 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 631 ) 632 } 633 634 for ((x,y) <- io.in.zip(io.out)) { 635 printRenameInfo(x, y) 636 } 637 638 io.out.map { case x => 639 when(x.valid && x.bits.rfWen){ 640 assert(x.bits.ldest =/= 0.U, "rfWen cannot be 1 when Int regfile ldest is 0") 641 } 642 } 643 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 644 // bad speculation 645 val recStall = io.redirect.valid || io.rabCommits.isWalk 646 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.rabCommits.isWalk && debugRedirect.debugIsCtrl) 647 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.rabCommits.isWalk && debugRedirect.debugIsMemVio) 648 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 649 XSPerfAccumulate("recovery_stall", recStall) 650 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 651 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 652 XSPerfAccumulate("other_recovery_stall", otherRecStall) 653 // freelist stall 654 val notRecStall = !io.out.head.valid && !recStall 655 val intFlStall = notRecStall && inHeadValid && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 656 val fpFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 657 val vecFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 658 val v0FlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 659 val vlFlStall = notRecStall && inHeadValid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 660 val multiFlStall = notRecStall && inHeadValid && (PopCount(Cat( 661 !intFreeList.io.canAllocate, 662 !fpFreeList.io.canAllocate, 663 !vecFreeList.io.canAllocate, 664 !v0FreeList.io.canAllocate, 665 !vlFreeList.io.canAllocate, 666 )) > 1.U) 667 // other stall 668 val otherStall = notRecStall && !intFlStall && !fpFlStall && !vecFlStall && !v0FlStall && !vlFlStall && !multiFlStall 669 670 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 671 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 672 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 673 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 674 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 675 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 676 intFlStall -> TopDownCounters.IntFlStall.id.U, 677 fpFlStall -> TopDownCounters.FpFlStall.id.U, 678 vecFlStall -> TopDownCounters.VecFlStall.id.U, 679 v0FlStall -> TopDownCounters.V0FlStall.id.U, 680 vlFlStall -> TopDownCounters.VlFlStall.id.U, 681 multiFlStall -> TopDownCounters.MultiFlStall.id.U, 682 ) 683 )) 684 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 685 out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) 686 } 687 688 XSDebug(io.rabCommits.isWalk, p"Walk Recovery Enabled\n") 689 XSDebug(io.rabCommits.isWalk, p"validVec:${Binary(io.rabCommits.walkValid.asUInt)}\n") 690 for (i <- 0 until RabCommitWidth) { 691 val info = io.rabCommits.info(i) 692 XSDebug(io.rabCommits.isWalk && io.rabCommits.walkValid(i), p"[#$i walk info] " + 693 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen} v0Wen:${info.v0Wen} vlWen:${info.vlWen}") 694 } 695 696 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 697 698 XSPerfAccumulate("in_valid_count", PopCount(io.in.map(_.valid))) 699 XSPerfAccumulate("in_fire_count", PopCount(io.in.map(_.fire))) 700 XSPerfAccumulate("in_valid_not_ready_count", PopCount(io.in.map(x => x.valid && !x.ready))) 701 XSPerfAccumulate("wait_cycle", !io.in.head.valid && dispatchCanAcc) 702 703 // These stall reasons could overlap each other, but we configure the priority as fellows. 704 // walk stall > dispatch stall > int freelist stall > fp freelist stall 705 private val inHeadStall = io.in.head match { case x => x.valid && !x.ready } 706 private val stallForWalk = inHeadValid && io.rabCommits.isWalk 707 private val stallForDispatch = inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc 708 private val stallForIntFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate 709 private val stallForFpFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate 710 private val stallForVecFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate 711 private val stallForV0FL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate 712 private val stallForVlFL = inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate 713 XSPerfAccumulate("stall_cycle", inHeadStall) 714 XSPerfAccumulate("stall_cycle_walk", stallForWalk) 715 XSPerfAccumulate("stall_cycle_dispatch", stallForDispatch) 716 XSPerfAccumulate("stall_cycle_int", stallForIntFL) 717 XSPerfAccumulate("stall_cycle_fp", stallForFpFL) 718 XSPerfAccumulate("stall_cycle_vec", stallForVecFL) 719 XSPerfAccumulate("stall_cycle_vec", stallForV0FL) 720 XSPerfAccumulate("stall_cycle_vec", stallForVlFL) 721 722 XSPerfHistogram("in_valid_range", PopCount(io.in.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 723 XSPerfHistogram("in_fire_range", PopCount(io.in.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 724 XSPerfHistogram("out_valid_range", PopCount(io.out.map(_.valid)), true.B, 0, DecodeWidth + 1, 1) 725 XSPerfHistogram("out_fire_range", PopCount(io.out.map(_.fire)), true.B, 0, DecodeWidth + 1, 1) 726 727 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 728 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 729 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 730 731 val renamePerf = Seq( 732 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 733 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 734 ("rename_stall ", inHeadStall), 735 ("rename_stall_cycle_walk ", inHeadValid && io.rabCommits.isWalk), 736 ("rename_stall_cycle_dispatch", inHeadValid && !io.rabCommits.isWalk && !dispatchCanAcc), 737 ("rename_stall_cycle_int ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !intFreeList.io.canAllocate), 738 ("rename_stall_cycle_fp ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !fpFreeList.io.canAllocate), 739 ("rename_stall_cycle_vec ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && v0FreeList.io.canAllocate && vlFreeList.io.canAllocate && !vecFreeList.io.canAllocate), 740 ("rename_stall_cycle_v0 ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && vlFreeList.io.canAllocate && !v0FreeList.io.canAllocate), 741 ("rename_stall_cycle_vl ", inHeadValid && !io.rabCommits.isWalk && dispatchCanAcc && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && vecFreeList.io.canAllocate && v0FreeList.io.canAllocate && !vlFreeList.io.canAllocate), 742 ) 743 val intFlPerf = intFreeList.getPerfEvents 744 val fpFlPerf = fpFreeList.getPerfEvents 745 val vecFlPerf = vecFreeList.getPerfEvents 746 val v0FlPerf = v0FreeList.getPerfEvents 747 val vlFlPerf = vlFreeList.getPerfEvents 748 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf ++ vecFlPerf ++ v0FlPerf ++ vlFlPerf 749 generatePerfEvent() 750} 751