1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.utils.XSInfo 7 8class Rename extends XSModule { 9 val io = IO(new Bundle() { 10 val redirect = Flipped(ValidIO(new Redirect)) 11 val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) 12 val wbIntResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 13 val wbFpResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 14 val intRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 15 val fpRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 16 val intPregRdy = Vec(NRReadPorts, Output(Bool())) 17 val fpPregRdy = Vec(NRReadPorts, Output(Bool())) 18 // from decode buffer 19 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 20 // to dispatch1 21 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 22 }) 23 24 val debug_exception = io.redirect.valid && io.redirect.bits.isException 25 val debug_walk = io.roqCommits.map(_.bits.isWalk).reduce(_ || _) 26 val debug_norm = !(debug_exception || debug_walk) 27 28 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 29 XSInfo( 30 debug_norm, 31 p"pc:${Hexadecimal(in.bits.cf.pc)} v:${in.valid} rdy:${in.ready} " + 32 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 33 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 34 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 35 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 36 p"old_pdest:${out.bits.old_pdest}\n" 37 ) 38 } 39 40 for((x,y) <- io.in.zip(io.out)){ 41 printRenameInfo(x, y) 42 } 43 44 val fpFreeList, intFreeList = Module(new FreeList).io 45 val fpRat = Module(new RenameTable(float = true)).io 46 val intRat = Module(new RenameTable(float = false)).io 47 val fpBusyTable, intBusyTable = Module(new BusyTable).io 48 49 fpFreeList.redirect := io.redirect 50 intFreeList.redirect := io.redirect 51 52 val flush = io.redirect.valid && io.redirect.bits.isException 53 fpRat.flush := flush 54 intRat.flush := flush 55 fpBusyTable.flush := flush 56 intBusyTable.flush := flush 57 58 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 59 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 60 } 61 62 val uops = Wire(Vec(RenameWidth, new MicroOp)) 63 64 uops.foreach( uop => { 65 uop.brMask := DontCare 66 uop.brTag := DontCare 67 uop.src1State := DontCare 68 uop.src2State := DontCare 69 uop.src3State := DontCare 70 uop.roqIdx := DontCare 71 }) 72 73 var last_can_alloc = WireInit(true.B) 74 for(i <- 0 until RenameWidth){ 75 uops(i).cf := io.in(i).bits.cf 76 uops(i).ctrl := io.in(i).bits.ctrl 77 78 // alloc a new phy reg 79 val needFpDest = io.in(i).valid && needDestReg(fp = true, io.in(i).bits) 80 val needIntDest = io.in(i).valid && needDestReg(fp = false, io.in(i).bits) 81 fpFreeList.allocReqs(i) := needFpDest && last_can_alloc && io.out(i).ready 82 intFreeList.allocReqs(i) := needIntDest && last_can_alloc && io.out(i).ready 83 val fpCanAlloc = fpFreeList.canAlloc(i) 84 val intCanAlloc = intFreeList.canAlloc(i) 85 val this_can_alloc = Mux(needIntDest, intCanAlloc, fpCanAlloc) 86 io.in(i).ready := this_can_alloc 87 last_can_alloc = last_can_alloc && this_can_alloc 88 uops(i).pdest := Mux(needIntDest, intFreeList.pdests(i), fpFreeList.pdests(i)) 89 uops(i).freelistAllocPtr := Mux(needIntDest, intFreeList.allocPtrs(i), fpFreeList.allocPtrs(i)) 90 91 io.out(i).valid := io.in(i).fire() 92 io.out(i).bits := uops(i) 93 94 // write rename table 95 def writeRat(fp: Boolean) = { 96 val rat = if(fp) fpRat else intRat 97 val freeList = if(fp) fpFreeList else intFreeList 98 val busyTable = if(fp) fpBusyTable else intBusyTable 99 // speculative inst write 100 val specWen = freeList.allocReqs(i) && freeList.canAlloc(i) 101 // walk back write 102 val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop) 103 val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk 104 105 rat.specWritePorts(i).wen := specWen || walkWen 106 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest) 107 rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest) 108 109 XSInfo(walkWen, 110 {if(fp) "fp" else "int "} + p"walk: pc:${Hexadecimal(uops(i).cf.pc)}" + 111 p" ldst:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n" 112 ) 113 114 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk 115 rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest 116 rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest 117 118 XSInfo(rat.archWritePorts(i).wen, 119 {if(fp) "fp" else "int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 120 p" pdest:${rat.archWritePorts(i).wdata}\n" 121 ) 122 123 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 124 freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest 125 126 // set phy reg status to busy 127 busyTable.allocPregs(i).valid := specWen 128 busyTable.allocPregs(i).bits := freeList.pdests(i) 129 } 130 131 writeRat(fp = false) 132 writeRat(fp = true) 133 134 // read rename table 135 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 136 val rat = if(fp) fpRat else intRat 137 val srcCnt = lsrcList.size 138 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 139 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 140 for(k <- 0 until srcCnt+1){ 141 val rportIdx = i * (srcCnt+1) + k 142 if(k != srcCnt){ 143 rat.readPorts(rportIdx).addr := lsrcList(k) 144 psrcVec(k) := rat.readPorts(rportIdx).rdata 145 } else { 146 rat.readPorts(rportIdx).addr := ldest 147 old_pdest := rat.readPorts(rportIdx).rdata 148 } 149 } 150 (psrcVec, old_pdest) 151 } 152 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 153 val ldest = uops(i).ctrl.ldest 154 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 155 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 156 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 157 uops(i).psrc2 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 158 uops(i).psrc3 := fpPhySrcVec(2) 159 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 160 } 161 162 163 def updateBusyTable(fp: Boolean) = { 164 val wbResults = if(fp) io.wbFpResults else io.wbIntResults 165 val busyTable = if(fp) fpBusyTable else intBusyTable 166 for((wb, setPhyRegRdy) <- wbResults.zip(busyTable.wbPregs)){ 167 setPhyRegRdy.valid := wb.valid && needDestReg(fp, wb.bits.uop) 168 setPhyRegRdy.bits := wb.bits.uop.pdest 169 } 170 } 171 172 updateBusyTable(false) 173 updateBusyTable(true) 174 175 intBusyTable.rfReadAddr <> io.intRfReadAddr 176 intBusyTable.pregRdy <> io.intPregRdy 177 fpBusyTable.rfReadAddr <> io.fpRfReadAddr 178 fpBusyTable.pregRdy <> io.fpPregRdy 179} 180