xref: /XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala (revision 6639e9a467468f4e1b05a25a5de4500772aedeb1) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16*
17*
18* Acknowledgement
19*
20* This implementation is inspired by several key papers:
21* [1] Fernando Latorre, Grigorios Magklis, Jose González, Pedro Chaparro, and Antonio González. "[Crob: implementing a
22* large instruction window through compression.](https://doi.org/10.1007/978-3-642-19448-1_7)" Transactions on
23* High-Performance Embedded Architectures and Compilers III: 115-134. Berlin, Heidelberg: Springer Berlin Heidelberg.
24* 2011.
25***************************************************************************************/
26
27package xiangshan.backend.rename
28
29import org.chipsalliance.cde.config.Parameters
30import chisel3.Bundle
31import xiangshan.backend.Bundles.DecodedInst
32import xiangshan.XSModule
33import chisel3._
34import chisel3.util._
35import freechips.rocketchip.rocket.DecodeLogic
36import xiangshan._
37
38class CompressUnit(implicit p: Parameters) extends XSModule{
39  val io = IO(new Bundle {
40    val in = Vec(RenameWidth, Flipped(Valid(new DecodedInst)))
41    val out = new Bundle {
42      val needRobFlags = Vec(RenameWidth, Output(Bool()))
43      val instrSizes = Vec(RenameWidth, Output(UInt(log2Ceil(RenameWidth + 1).W)))
44      val masks = Vec(RenameWidth, Output(UInt(RenameWidth.W)))
45    }
46  })
47
48  val noExc = io.in.map(in => !in.bits.exceptionVec.asUInt.orR && !TriggerAction.isDmode(in.bits.trigger))
49  val uopCanCompress = io.in.map(_.bits.canRobCompress)
50  val canCompress = io.in.zip(noExc).zip(uopCanCompress).map { case ((in, noExc), canComp) =>
51    in.valid && !CommitType.isFused(in.bits.commitType) && in.bits.lastUop && noExc && canComp
52  }
53
54  val compressTable = (0 until 1 << RenameWidth).map { case keyCandidate =>
55    // padding 0s at each side for convenience
56    val key = 0 +: (0 until RenameWidth).map(idx => (keyCandidate >> idx) & 1) :+ 0
57    // count 1s on the left side of key (including itself)
58    def cntL(idx: Int): Int = (if (key(idx - 1) == 1) cntL(idx - 1) else 0) + key(idx)
59    // count 1s on the right side of key (including itself)
60    def cntR(idx: Int): Int = (if (key(idx + 1) == 1) cntR(idx + 1) else 0) + key(idx)
61    // the last instruction among consecutive rob-compressed instructions is marked
62    val needRobs = (0 until RenameWidth).map(idx => ~(key.tail(idx) & key.tail(idx + 1)) & 1)
63    // how many instructions are rob-compressed with this instruction (including itself)
64    val uopSizes = (1 to RenameWidth).map(idx => if (key(idx) == 0) 1 else cntL(idx) + cntR(idx) - 1)
65    // which instructions are rob-compressed with this instruction
66    val masks = uopSizes.zip(1 to RenameWidth).map { case (size, idx) => // compress masks
67      if (key(idx) == 0) Seq.fill(RenameWidth)(0).updated(idx - 1, 1)
68      else Seq.fill(RenameWidth)(0).patch(idx - cntL(idx), Seq.fill(size)(1), size)
69    }
70
71    println("[Rename.Compress]" +
72      " i: "        + keyCandidate +
73      " key: "      + key.tail.dropRight(1) +
74      " needRobs: " + needRobs +
75      " uopSizes: " + uopSizes +
76      " masks: "    + masks.map(_.map(_.toBinaryString).reduce(_ + _))
77    )
78
79    val keyBitPat = BitPat(keyCandidate.U)
80    val needRobBitPats = needRobs.map(x => BitPat(x.U))
81    val uopSizeBitPats = uopSizes.map(x => BitPat(x.U))
82    val maskBitPats = masks.map(m => BitPat(m.foldRight(0)(_ | _ << 1).U))
83
84    (keyBitPat -> (needRobBitPats ++ uopSizeBitPats ++ maskBitPats))
85  }
86
87  val default = Seq.fill(3 * RenameWidth)(BitPat.N())
88  val decoder = DecodeLogic(VecInit(canCompress).asUInt, default, compressTable)
89  (io.out.needRobFlags ++ io.out.instrSizes ++ io.out.masks).zip(decoder).foreach {
90    case (sink, source) => sink := source
91  }
92}
93