1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.{ParallelOR, XSDebug} 7 8class BusyTable extends XSModule { 9 val io = IO(new Bundle() { 10 val flush = Input(Bool()) 11 // set preg state to busy 12 val allocPregs = Vec(RenameWidth, Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 13 // set preg state to ready (write back regfile + roq walk) 14 val wbPregs = Vec(NRWritePorts + CommitWidth, Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 15 // read preg state 16 val rfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 17 val pregRdy = Vec(NRReadPorts, Output(Bool())) 18 }) 19 20 val table = RegInit(VecInit(Seq.fill(NRPhyRegs)(false.B))) 21 22 for((raddr, rdy) <- io.rfReadAddr.zip(io.pregRdy)){ 23 rdy := !table(raddr) || ParallelOR(io.wbPregs.map(wb => wb.valid && (wb.bits===raddr))).asBool() 24 } 25 26 for((alloc, i) <- io.allocPregs.zipWithIndex){ 27 when(alloc.valid){ 28 table(alloc.bits) := true.B 29 } 30 XSDebug(alloc.valid, "Allocate %d\n", alloc.bits) 31 } 32 33 for((wb, i) <- io.wbPregs.zipWithIndex){ 34 when(wb.valid){ 35 table(wb.bits) := false.B 36 } 37 XSDebug(wb.valid, "writeback %d\n", wb.bits) 38 } 39 40 when(io.flush){ 41 table.foreach(_ := false.B) 42 } 43 44 for (i <- 0 until NRPhyRegs) { 45 XSDebug(table(i), "%d is busy\n", i.U) 46 } 47} 48