1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6 7class BusyTable extends XSModule { 8 val io = IO(new Bundle() { 9 val flush = Input(Bool()) 10 // set preg state to busy 11 val allocPregs = Vec(RenameWidth, Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 12 // set preg state to ready 13 val wbPregs = Vec(NRWritePorts, Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 14 // read preg state 15 val rfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 16 val pregRdy = Vec(NRReadPorts, Output(Bool())) 17 }) 18 19 val table = RegInit(VecInit(Seq.fill(NRPhyRegs)(false.B))) 20 21 for((raddr, rdy) <- io.rfReadAddr.zip(io.pregRdy)){ 22 rdy := !table(raddr) 23 } 24 25 for((alloc, i) <- io.allocPregs.zipWithIndex){ 26 when(alloc.valid){ 27 table(alloc.bits) := true.B 28 } 29 } 30 31 for((wb, i) <- io.wbPregs.zipWithIndex){ 32 when(wb.valid){ 33 table(wb.bits) := false.B 34 } 35 } 36 37 when(io.flush){ 38 table.foreach(_ := false.B) 39 } 40} 41