1package xiangshan.backend.regfile 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6 7class RfReadPort extends XSBundle { 8 val addr = Input(UInt(PhyRegIdxWidth.W)) 9 val data = Output(UInt((XLEN + 1).W)) 10} 11 12class RfWritePort extends XSBundle { 13 val wen = Input(Bool()) 14 val addr = Input(UInt(PhyRegIdxWidth.W)) 15 val data = Input(UInt((XLEN + 1).W)) 16} 17 18class Regfile 19( 20 numReadPorts: Int, 21 numWirtePorts: Int, 22 hasZero: Boolean, 23 len: Int 24) extends XSModule { 25 val io = IO(new Bundle() { 26 val readPorts = Vec(numReadPorts, new RfReadPort) 27 val writePorts = Vec(numWirtePorts, new RfWritePort) 28 }) 29 30 31 32 if (!env.FPGAPlatform) { 33 34 35 val mem = Mem(NRPhyRegs, UInt(len.W)) 36 37 for(r <- io.readPorts){ 38 val addr_reg = RegNext(r.addr) 39 r.data := {if(hasZero) Mux(addr_reg===0.U, 0.U, mem(addr_reg)) else mem(addr_reg)} 40 } 41 42 for(w <- io.writePorts){ 43 when(w.wen){ 44 mem(w.addr) := w.data 45 } 46 } 47 48 val debugArchRat = WireInit(VecInit(Seq.fill(32)(0.U(PhyRegIdxWidth.W)))) 49 ExcitingUtils.addSink( 50 debugArchRat, 51 if(hasZero) "DEBUG_INI_ARCH_RAT" else "DEBUG_FP_ARCH_RAT", 52 ExcitingUtils.Debug 53 ) 54 55 val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map( 56 x => if(hasZero){ 57 if(x._2 == 0) 0.U else mem(x._1) 58 } else ieee(mem(x._1)) 59 ))) 60 ExcitingUtils.addSource( 61 debugArchReg, 62 if(hasZero) "DEBUG_INT_ARCH_REG" else "DEBUG_FP_ARCH_REG", 63 ExcitingUtils.Debug 64 ) 65 } else { 66 67 val regfile = Module(new regfile_160x64_10w16r_sim) 68 69 regfile.io.clk := this.clock 70 regfile.io.gpr := hasZero.B 71 72 regfile.io.wen0 := io.writePorts(0).wen 73 regfile.io.waddr0 := io.writePorts(0).addr 74 regfile.io.wdata0 := io.writePorts(0).data 75 76 regfile.io.wen1 := io.writePorts(1).wen 77 regfile.io.waddr1 := io.writePorts(1).addr 78 regfile.io.wdata1 := io.writePorts(1).data 79 80 regfile.io.wen2 := io.writePorts(2).wen 81 regfile.io.waddr2 := io.writePorts(2).addr 82 regfile.io.wdata2 := io.writePorts(2).data 83 84 regfile.io.wen3 := io.writePorts(3).wen 85 regfile.io.waddr3 := io.writePorts(3).addr 86 regfile.io.wdata3 := io.writePorts(3).data 87 88 regfile.io.wen4 := io.writePorts(4).wen 89 regfile.io.waddr4 := io.writePorts(4).addr 90 regfile.io.wdata4 := io.writePorts(4).data 91 92 regfile.io.wen5 := io.writePorts(5).wen 93 regfile.io.waddr5 := io.writePorts(5).addr 94 regfile.io.wdata5 := io.writePorts(5).data 95 96 regfile.io.wen6 := io.writePorts(6).wen 97 regfile.io.waddr6 := io.writePorts(6).addr 98 regfile.io.wdata6 := io.writePorts(6).data 99 100 regfile.io.wen7 := io.writePorts(7).wen 101 regfile.io.waddr7 := io.writePorts(7).addr 102 regfile.io.wdata7 := io.writePorts(7).data 103 104 regfile.io.wen8 := false.B //io.writePorts(8).wen 105 regfile.io.waddr8 := DontCare //io.writePorts(8).addr 106 regfile.io.wdata8 := DontCare //io.writePorts(8).data 107 108 regfile.io.wen9 := false.B //io.writePorts(9).wen 109 regfile.io.waddr9 := DontCare //io.writePorts(9).addr 110 regfile.io.wdata9 := DontCare //io.writePorts(9).data 111 112 113 regfile.io.raddr0 := io.readPorts(0).addr 114 regfile.io.raddr1 := io.readPorts(1).addr 115 regfile.io.raddr2 := io.readPorts(2).addr 116 regfile.io.raddr3 := io.readPorts(3).addr 117 regfile.io.raddr4 := io.readPorts(4).addr 118 regfile.io.raddr5 := io.readPorts(5).addr 119 regfile.io.raddr6 := io.readPorts(6).addr 120 regfile.io.raddr7 := io.readPorts(7).addr 121 regfile.io.raddr8 := io.readPorts(8).addr 122 regfile.io.raddr9 := io.readPorts(9).addr 123 regfile.io.raddr10 := io.readPorts(10).addr 124 regfile.io.raddr11 := io.readPorts(11).addr 125 regfile.io.raddr12 := io.readPorts(12).addr 126 regfile.io.raddr13 := io.readPorts(13).addr 127 regfile.io.raddr14 := DontCare //io.readPorts(14).addr 128 regfile.io.raddr15 := DontCare //io.readPorts(15).addr 129 130 io.readPorts(0).data := regfile.io.rdata0 131 io.readPorts(1).data := regfile.io.rdata1 132 io.readPorts(2).data := regfile.io.rdata2 133 io.readPorts(3).data := regfile.io.rdata3 134 io.readPorts(4).data := regfile.io.rdata4 135 io.readPorts(5).data := regfile.io.rdata5 136 io.readPorts(6).data := regfile.io.rdata6 137 io.readPorts(7).data := regfile.io.rdata7 138 io.readPorts(8).data := regfile.io.rdata8 139 io.readPorts(9).data := regfile.io.rdata9 140 io.readPorts(10).data := regfile.io.rdata10 141 io.readPorts(11).data := regfile.io.rdata11 142 io.readPorts(12).data := regfile.io.rdata12 143 io.readPorts(13).data := regfile.io.rdata13 144 } 145 146} 147 148class regfile_160x64_10w16r_sim extends BlackBox with HasBlackBoxResource { 149 150 val io = IO(new Bundle{ 151 val clk = Input(Clock()) 152 val gpr = Input(Bool()) 153 154 // write 155 val wen0, wen1, wen2, wen3, wen4, wen5, wen6, wen7, wen8, wen9 = Input(Bool()) 156 val waddr0, waddr1, waddr2, waddr3, waddr4, waddr5, waddr6, waddr7, waddr8, waddr9 = Input(UInt(8.W)) 157 val wdata0, wdata1, wdata2, wdata3, wdata4, wdata5, wdata6, wdata7, wdata8, wdata9 = Input(UInt(64.W)) 158 159 // read 160 val raddr0, raddr1, raddr2, raddr3, raddr4, raddr5, raddr6, raddr7 = Input(UInt(8.W)) 161 val raddr8, raddr9, raddr10, raddr11, raddr12, raddr13, raddr14, raddr15 = Input(UInt(8.W)) 162 val rdata0, rdata1, rdata2, rdata3, rdata4, rdata5, rdata6, rdata7 = Output(UInt(64.W)) 163 val rdata8, rdata9, rdata10, rdata11, rdata12, rdata13, rdata14, rdata15 = Output(UInt(64.W)) 164 }) 165 166 val vsrc = "/vsrc/regfile_160x64_10w16r_sim.v" 167 println(s"Regfile: Using verilog source at: $vsrc") 168 setResource(vsrc) 169 170} 171 172