1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.regfile 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.backend.datapath.DataConfig.{DataConfig, FpData, FpRegSrcDataSet, IntData, IntRegSrcDataSet, VecData, VecRegSrcDataSet, VfRegSrcDataSet} 24import xiangshan.backend.exu.ExeUnitParams 25 26class RfReadPort(dataWidth: Int, addrWidth: Int) extends Bundle { 27 val addr = Input(UInt(addrWidth.W)) 28 val data = Output(UInt(dataWidth.W)) 29} 30 31class RfWritePort(dataWidth: Int, addrWidth: Int) extends Bundle { 32 val wen = Input(Bool()) 33 val addr = Input(UInt(addrWidth.W)) 34 val data = Input(UInt(dataWidth.W)) 35} 36 37class RfReadPortWithConfig(val rfReadDataCfg: DataConfig, addrWidth: Int) extends Bundle { 38 val addr: UInt = Input(UInt(addrWidth.W)) 39 val srcType: UInt = Input(UInt(3.W)) 40 41 def readInt: Boolean = IntRegSrcDataSet.contains(rfReadDataCfg) 42 def readFp : Boolean = FpRegSrcDataSet .contains(rfReadDataCfg) 43 def readVec: Boolean = VecRegSrcDataSet.contains(rfReadDataCfg) 44 def readVf : Boolean = VfRegSrcDataSet .contains(rfReadDataCfg) 45} 46 47class RfWritePortWithConfig(val rfWriteDataCfg: DataConfig, addrWidth: Int) extends Bundle { 48 val wen = Input(Bool()) 49 val addr = Input(UInt(addrWidth.W)) 50 val data = Input(UInt(rfWriteDataCfg.dataWidth.W)) 51 val intWen = Input(Bool()) 52 val fpWen = Input(Bool()) 53 val vecWen = Input(Bool()) 54 def writeInt: Boolean = rfWriteDataCfg.isInstanceOf[IntData] 55 def writeFp : Boolean = rfWriteDataCfg.isInstanceOf[FpData] 56 def writeVec: Boolean = rfWriteDataCfg.isInstanceOf[VecData] 57} 58 59class Regfile 60( 61 name: String, 62 numPregs: Int, 63 numReadPorts: Int, 64 numWritePorts: Int, 65 hasZero: Boolean, 66 len: Int, 67 width: Int, 68 bankNum: Int = 1, 69) extends Module { 70 val io = IO(new Bundle() { 71 val readPorts = Vec(numReadPorts, new RfReadPort(len, width)) 72 val writePorts = Vec(numWritePorts, new RfWritePort(len, width)) 73 val debug_rports = Vec(65, new RfReadPort(len, width)) 74 }) 75 76 println(name + ": size:" + numPregs + " read: " + numReadPorts + " write: " + numWritePorts) 77 78 val mem = Reg(Vec(numPregs, UInt(len.W))) 79 for (r <- io.readPorts) { 80 if (bankNum == 1) { 81 r.data := mem(RegNext(r.addr)) 82 } 83 else { 84 val banks = (0 until bankNum).map { case i => 85 mem.zipWithIndex.filter{ case (m, index) => (index % bankNum) == i }.map(_._1) 86 } 87 val bankWidth = bankNum.U.getWidth - 1 88 val hitBankWire = VecInit((0 until bankNum).map { case i => r.addr(bankWidth - 1, 0) === i.U }) 89 val hitBankReg = Reg(Vec(bankNum, Bool())) 90 hitBankReg := hitBankWire 91 val banksRdata = Wire(Vec(bankNum, UInt(len.W))) 92 for (i <- 0 until bankNum) { 93 banksRdata(i) := RegEnable(VecInit(banks(i))(r.addr(r.addr.getWidth - 1, bankWidth)), hitBankWire(i)) 94 } 95 r.data := Mux1H(hitBankReg, banksRdata) 96 } 97 } 98 val writePorts = io.writePorts 99 for (i <- writePorts.indices) { 100 if (i < writePorts.size-1) { 101 val hasSameWrite = writePorts.drop(i + 1).map(w => w.wen && w.addr === writePorts(i).addr && writePorts(i).wen).reduce(_ || _) 102 assert(!hasSameWrite, "RegFile two or more writePorts write same addr") 103 } 104 } 105 for (i <- mem.indices) { 106 if (hasZero && i == 0) { 107 mem(i) := 0.U 108 } 109 else { 110 val wenOH = VecInit(io.writePorts.map(w => w.wen && w.addr === i.U)) 111 val wData = Mux1H(wenOH, io.writePorts.map(_.data)) 112 when(wenOH.asUInt.orR) { 113 mem(i) := wData 114 } 115 } 116 } 117 118 for (rport <- io.debug_rports) { 119 val zero_rdata = Mux(rport.addr === 0.U, 0.U, mem(rport.addr)) 120 rport.data := (if (hasZero) zero_rdata else mem(rport.addr)) 121 } 122} 123 124object Regfile { 125 // non-return version 126 def apply( 127 name : String, 128 numEntries : Int, 129 raddr : Seq[UInt], 130 rdata : Vec[UInt], 131 wen : Seq[Bool], 132 waddr : Seq[UInt], 133 wdata : Seq[UInt], 134 hasZero : Boolean, 135 withReset : Boolean = false, 136 bankNum : Int = 1, 137 debugReadAddr: Option[Seq[UInt]], 138 debugReadData: Option[Vec[UInt]], 139 )(implicit p: Parameters): Unit = { 140 val numReadPorts = raddr.length 141 val numWritePorts = wen.length 142 require(wen.length == waddr.length) 143 require(wen.length == wdata.length) 144 val dataBits = wdata.map(_.getWidth).min 145 require(wdata.map(_.getWidth).min == wdata.map(_.getWidth).max, s"dataBits != $dataBits") 146 val addrBits = waddr.map(_.getWidth).min 147 require(waddr.map(_.getWidth).min == waddr.map(_.getWidth).max, s"addrBits != $addrBits") 148 149 val regfile = Module(new Regfile(name, numEntries, numReadPorts, numWritePorts, hasZero, dataBits, addrBits, bankNum)) 150 rdata := regfile.io.readPorts.zip(raddr).map { case (rport, addr) => 151 rport.addr := addr 152 rport.data 153 } 154 155 regfile.io.writePorts.zip(wen).zip(waddr).zip(wdata).foreach{ case (((wport, en), addr), data) => 156 wport.wen := en 157 wport.addr := addr 158 wport.data := data 159 } 160 if (withReset) { 161 val numResetCycles = math.ceil(numEntries / numWritePorts).toInt 162 val resetCounter = RegInit(numResetCycles.U) 163 val resetWaddr = RegInit(VecInit((0 until numWritePorts).map(_.U(log2Up(numEntries + 1).W)))) 164 val inReset = resetCounter =/= 0.U 165 when (inReset) { 166 resetCounter := resetCounter - 1.U 167 resetWaddr := VecInit(resetWaddr.map(_ + numWritePorts.U)) 168 } 169 when (!inReset) { 170 resetWaddr.map(_ := 0.U) 171 } 172 for ((wport, i) <- regfile.io.writePorts.zipWithIndex) { 173 wport.wen := inReset || wen(i) 174 wport.addr := Mux(inReset, resetWaddr(i), waddr(i)) 175 wport.data := wdata(i) 176 } 177 } 178 179 require(debugReadAddr.nonEmpty == debugReadData.nonEmpty, "Both debug addr and data bundles should be empty or not") 180 regfile.io.debug_rports := DontCare 181 if (debugReadAddr.nonEmpty && debugReadData.nonEmpty) { 182 debugReadData.get := VecInit(regfile.io.debug_rports.zip(debugReadAddr.get).map { case (rport, addr) => 183 rport.addr := addr 184 rport.data 185 }) 186 } 187 } 188} 189 190object IntRegFile { 191 // non-return version 192 def apply( 193 name : String, 194 numEntries : Int, 195 raddr : Seq[UInt], 196 rdata : Vec[UInt], 197 wen : Seq[Bool], 198 waddr : Seq[UInt], 199 wdata : Seq[UInt], 200 debugReadAddr: Option[Seq[UInt]], 201 debugReadData: Option[Vec[UInt]], 202 withReset : Boolean = false, 203 bankNum : Int, 204 )(implicit p: Parameters): Unit = { 205 Regfile( 206 name, numEntries, raddr, rdata, wen, waddr, wdata, 207 hasZero = true, withReset, bankNum, debugReadAddr, debugReadData) 208 } 209} 210 211object VfRegFile { 212 // non-return version 213 def apply( 214 name : String, 215 numEntries : Int, 216 splitNum : Int, 217 raddr : Seq[UInt], 218 rdata : Vec[UInt], 219 wen : Seq[Seq[Bool]], 220 waddr : Seq[UInt], 221 wdata : Seq[UInt], 222 debugReadAddr: Option[Seq[UInt]], 223 debugReadData: Option[Vec[UInt]], 224 withReset : Boolean = false, 225 )(implicit p: Parameters): Unit = { 226 require(splitNum >= 1, "splitNum should be no less than 1") 227 require(splitNum == wen.length, "splitNum should be equal to length of wen vec") 228 if (splitNum == 1) { 229 Regfile( 230 name, numEntries, raddr, rdata, wen.head, waddr, wdata, 231 hasZero = false, withReset, bankNum = 1, debugReadAddr, debugReadData) 232 } else { 233 val dataWidth = 64 234 val numReadPorts = raddr.length 235 require(splitNum > 1 && wdata.head.getWidth == dataWidth * splitNum) 236 val wdataVec = Wire(Vec(splitNum, Vec(wdata.length, UInt(dataWidth.W)))) 237 val rdataVec = Wire(Vec(splitNum, Vec(raddr.length, UInt(dataWidth.W)))) 238 val debugRDataVec: Option[Vec[Vec[UInt]]] = debugReadData.map(x => Wire(Vec(splitNum, Vec(x.length, UInt(dataWidth.W))))) 239 for (i <- 0 until splitNum) { 240 wdataVec(i) := wdata.map(_ ((i + 1) * dataWidth - 1, i * dataWidth)) 241 Regfile( 242 name + s"Part${i}", numEntries, raddr, rdataVec(i), wen(i), waddr, wdataVec(i), 243 hasZero = false, withReset, bankNum = 1, debugReadAddr, debugRDataVec.map(_(i)) 244 ) 245 } 246 for (i <- 0 until rdata.length) { 247 rdata(i) := Cat(rdataVec.map(_ (i)).reverse) 248 } 249 if (debugReadData.nonEmpty) { 250 for (i <- 0 until debugReadData.get.length) { 251 debugReadData.get(i) := Cat(debugRDataVec.get.map(_ (i)).reverse) 252 } 253 } 254 } 255 } 256}