1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.regfile 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.backend.datapath.DataConfig.{DataConfig, FpData, FpRegSrcDataSet, IntData, IntRegSrcDataSet, VecData, VecRegSrcDataSet, VfRegSrcDataSet} 24import xiangshan.backend.Bundles.IssueQueueWakeUpBundle 25 26class RfReadPort(dataWidth: Int, addrWidth: Int) extends Bundle { 27 val addr = Input(UInt(addrWidth.W)) 28 val data = Output(UInt(dataWidth.W)) 29} 30 31class RfWritePort(dataWidth: Int, addrWidth: Int) extends Bundle { 32 val wen = Input(Bool()) 33 val addr = Input(UInt(addrWidth.W)) 34 val data = Input(UInt(dataWidth.W)) 35} 36 37class RfReadPortWithConfig(val rfReadDataCfg: DataConfig, addrWidth: Int) extends Bundle { 38 val addr: UInt = Input(UInt(addrWidth.W)) 39 val data: UInt = Output(UInt(rfReadDataCfg.dataWidth.W)) 40 val srcType: UInt = Input(UInt(3.W)) 41 42 def readInt: Boolean = IntRegSrcDataSet.contains(rfReadDataCfg) 43 def readFp : Boolean = FpRegSrcDataSet .contains(rfReadDataCfg) 44 def readVec: Boolean = VecRegSrcDataSet.contains(rfReadDataCfg) 45 def readVf : Boolean = VfRegSrcDataSet .contains(rfReadDataCfg) 46} 47 48class RfWritePortWithConfig(val rfWriteDataCfg: DataConfig, addrWidth: Int) extends Bundle { 49 val wen = Input(Bool()) 50 val addr = Input(UInt(addrWidth.W)) 51 val data = Input(UInt(rfWriteDataCfg.dataWidth.W)) 52 val intWen = Input(Bool()) 53 val fpWen = Input(Bool()) 54 val vecWen = Input(Bool()) 55 def writeInt: Boolean = rfWriteDataCfg.isInstanceOf[IntData] 56 def writeFp : Boolean = rfWriteDataCfg.isInstanceOf[FpData] 57 def writeVec: Boolean = rfWriteDataCfg.isInstanceOf[VecData] 58 59 def toWakeUpBundle: ValidIO[IssueQueueWakeUpBundle] = { 60 val wakeup = Wire(ValidIO(new IssueQueueWakeUpBundle(addrWidth))) 61 wakeup.bits.pdest := this.addr 62 wakeup.bits.rfWen := this.intWen && this.wen 63 wakeup.bits.fpWen := this.fpWen && this.wen 64 wakeup.bits.vecWen := this.vecWen && this.wen 65 wakeup.valid := this.wen 66 wakeup 67 } 68} 69 70class Regfile 71( 72 name: String, 73 numPregs: Int, 74 numReadPorts: Int, 75 numWritePorts: Int, 76 hasZero: Boolean, 77 len: Int, 78 width: Int, 79) extends Module { 80 val io = IO(new Bundle() { 81 val readPorts = Vec(numReadPorts, new RfReadPort(len, width)) 82 val writePorts = Vec(numWritePorts, new RfWritePort(len, width)) 83 val debug_rports = Vec(65, new RfReadPort(len, width)) 84 }) 85 86 println(name + ": size:" + numPregs + " read: " + numReadPorts + " write: " + numWritePorts) 87 88 val mem = Reg(Vec(numPregs, UInt(len.W))) 89 for (r <- io.readPorts) { 90 val rdata = if (hasZero) Mux(r.addr === 0.U, 0.U, mem(r.addr)) else mem(r.addr) 91 r.data := RegNext(rdata) 92 } 93 for (w <- io.writePorts) { 94 when(w.wen) { 95 mem(w.addr) := w.data 96 } 97 } 98 99 for (rport <- io.debug_rports) { 100 val zero_rdata = Mux(rport.addr === 0.U, 0.U, mem(rport.addr)) 101 rport.data := (if (hasZero) zero_rdata else mem(rport.addr)) 102 } 103} 104 105object Regfile { 106 // non-return version 107 def apply( 108 name : String, 109 numEntries : Int, 110 raddr : Seq[UInt], 111 rdata : Vec[UInt], 112 wen : Seq[Bool], 113 waddr : Seq[UInt], 114 wdata : Seq[UInt], 115 hasZero : Boolean, 116 withReset : Boolean = false, 117 debugReadAddr: Option[Seq[UInt]], 118 debugReadData: Option[Vec[UInt]], 119 )(implicit p: Parameters): Unit = { 120 val numReadPorts = raddr.length 121 val numWritePorts = wen.length 122 require(wen.length == waddr.length) 123 require(wen.length == wdata.length) 124 val dataBits = wdata.map(_.getWidth).min 125 require(wdata.map(_.getWidth).min == wdata.map(_.getWidth).max, s"dataBits != $dataBits") 126 val addrBits = waddr.map(_.getWidth).min 127 require(waddr.map(_.getWidth).min == waddr.map(_.getWidth).max, s"addrBits != $addrBits") 128 129 val regfile = Module(new Regfile(name, numEntries, numReadPorts, numWritePorts, hasZero, dataBits, addrBits)) 130 rdata := regfile.io.readPorts.zip(raddr).map { case (rport, addr) => 131 rport.addr := addr 132 rport.data 133 } 134 135 regfile.io.writePorts.zip(wen).zip(waddr).zip(wdata).foreach{ case (((wport, en), addr), data) => 136 wport.wen := en 137 wport.addr := addr 138 wport.data := data 139 } 140 if (withReset) { 141 val numResetCycles = math.ceil(numEntries / numWritePorts).toInt 142 val resetCounter = RegInit(numResetCycles.U) 143 val resetWaddr = RegInit(VecInit((0 until numWritePorts).map(_.U(log2Up(numEntries + 1).W)))) 144 val inReset = resetCounter =/= 0.U 145 when (inReset) { 146 resetCounter := resetCounter - 1.U 147 resetWaddr := VecInit(resetWaddr.map(_ + numWritePorts.U)) 148 } 149 when (!inReset) { 150 resetWaddr.map(_ := 0.U) 151 } 152 for ((wport, i) <- regfile.io.writePorts.zipWithIndex) { 153 wport.wen := inReset || wen(i) 154 wport.addr := Mux(inReset, resetWaddr(i), waddr(i)) 155 wport.data := wdata(i) 156 } 157 } 158 159 require(debugReadAddr.nonEmpty == debugReadData.nonEmpty, "Both debug addr and data bundles should be empty or not") 160 regfile.io.debug_rports := DontCare 161 if (debugReadAddr.nonEmpty && debugReadData.nonEmpty) { 162 debugReadData.get := VecInit(regfile.io.debug_rports.zip(debugReadAddr.get).map { case (rport, addr) => 163 rport.addr := addr 164 rport.data 165 }) 166 } 167 } 168} 169 170object IntRegFile { 171 // non-return version 172 def apply( 173 name : String, 174 numEntries : Int, 175 raddr : Seq[UInt], 176 rdata : Vec[UInt], 177 wen : Seq[Bool], 178 waddr : Seq[UInt], 179 wdata : Seq[UInt], 180 debugReadAddr: Option[Seq[UInt]], 181 debugReadData: Option[Vec[UInt]], 182 withReset : Boolean = false, 183 )(implicit p: Parameters): Unit = { 184 Regfile( 185 name, numEntries, raddr, rdata, wen, waddr, wdata, 186 hasZero = true, withReset, debugReadAddr, debugReadData) 187 } 188} 189 190object VfRegFile { 191 // non-return version 192 def apply( 193 name : String, 194 numEntries : Int, 195 splitNum : Int, 196 raddr : Seq[UInt], 197 rdata : Vec[UInt], 198 wen : Seq[Seq[Bool]], 199 waddr : Seq[UInt], 200 wdata : Seq[UInt], 201 debugReadAddr: Option[Seq[UInt]], 202 debugReadData: Option[Vec[UInt]], 203 withReset : Boolean = false, 204 )(implicit p: Parameters): Unit = { 205 require(splitNum >= 1, "splitNum should be no less than 1") 206 require(splitNum == wen.length, "splitNum should be equal to length of wen vec") 207 if (splitNum == 1) { 208 Regfile( 209 name, numEntries, raddr, rdata, wen.head, waddr, wdata, 210 hasZero = false, withReset, debugReadAddr, debugReadData) 211 } else { 212 val dataWidth = 64 213 val numReadPorts = raddr.length 214 require(splitNum > 1 && wdata.head.getWidth == dataWidth * splitNum) 215 val wdataVec = Wire(Vec(splitNum, Vec(wdata.length, UInt(dataWidth.W)))) 216 val rdataVec = Wire(Vec(splitNum, Vec(raddr.length, UInt(dataWidth.W)))) 217 val debugRDataVec: Option[Vec[Vec[UInt]]] = debugReadData.map(x => Wire(Vec(splitNum, Vec(x.length, UInt(dataWidth.W))))) 218 for (i <- 0 until splitNum) { 219 wdataVec(i) := wdata.map(_ ((i + 1) * dataWidth - 1, i * dataWidth)) 220 Regfile( 221 name + s"Part${i}", numEntries, raddr, rdataVec(i), wen(i), waddr, wdataVec(i), 222 hasZero = false, withReset, debugReadAddr, debugRDataVec.map(_(i)) 223 ) 224 } 225 for (i <- 0 until rdata.length) { 226 rdata(i) := Cat(rdataVec.map(_ (i)).reverse) 227 } 228 if (debugReadData.nonEmpty) { 229 for (i <- 0 until debugReadData.get.length) { 230 debugReadData.get(i) := Cat(debugRDataVec.get.map(_ (i)).reverse) 231 } 232 } 233 } 234 } 235}