1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.regfile 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.exu.ExeUnitParams 25 26class RfReadPort(dataWidth: Int, addrWidth: Int) extends Bundle { 27 val addr = Input(UInt(addrWidth.W)) 28 val data = Output(UInt(dataWidth.W)) 29} 30 31class RfWritePort(dataWidth: Int, addrWidth: Int) extends Bundle { 32 val wen = Input(Bool()) 33 val addr = Input(UInt(addrWidth.W)) 34 val data = Input(UInt(dataWidth.W)) 35} 36 37class RfReadPortWithConfig(val rfReadDataCfg: DataConfig, addrWidth: Int) extends Bundle { 38 val addr: UInt = Input(UInt(addrWidth.W)) 39 val srcType: UInt = Input(UInt(3.W)) 40 41 def readInt: Boolean = IntRegSrcDataSet.contains(rfReadDataCfg) 42 def readFp : Boolean = FpRegSrcDataSet .contains(rfReadDataCfg) 43 def readVec: Boolean = VecRegSrcDataSet.contains(rfReadDataCfg) 44 def readVf : Boolean = VecRegSrcDataSet .contains(rfReadDataCfg) 45} 46 47class RfWritePortWithConfig(val rfWriteDataCfg: DataConfig, addrWidth: Int) extends Bundle { 48 val wen = Input(Bool()) 49 val addr = Input(UInt(addrWidth.W)) 50 val data = Input(UInt(rfWriteDataCfg.dataWidth.W)) 51 val intWen = Input(Bool()) 52 val fpWen = Input(Bool()) 53 val vecWen = Input(Bool()) 54 val v0Wen = Input(Bool()) 55 val vlWen = Input(Bool()) 56 def writeInt: Boolean = rfWriteDataCfg.isInstanceOf[IntData] 57 def writeFp : Boolean = rfWriteDataCfg.isInstanceOf[FpData] 58 def writeVec: Boolean = rfWriteDataCfg.isInstanceOf[VecData] 59 def writeV0 : Boolean = rfWriteDataCfg.isInstanceOf[V0Data] 60 def writeVl : Boolean = rfWriteDataCfg.isInstanceOf[VlData] 61} 62 63class Regfile 64( 65 name: String, 66 numPregs: Int, 67 numReadPorts: Int, 68 numWritePorts: Int, 69 hasZero: Boolean, 70 len: Int, 71 width: Int, 72 bankNum: Int = 1, 73 isVlRegfile: Boolean = false, 74) extends Module { 75 val io = IO(new Bundle() { 76 val readPorts = Vec(numReadPorts, new RfReadPort(len, width)) 77 val writePorts = Vec(numWritePorts, new RfWritePort(len, width)) 78 val debug_rports = Vec(65, new RfReadPort(len, width)) 79 }) 80 override def desiredName = name 81 println(name + ": size:" + numPregs + " read: " + numReadPorts + " write: " + numWritePorts) 82 83 val mem_0 = if (isVlRegfile) RegInit(0.U(len.W)) else Reg(UInt(len.W)) 84 val mem = Reg(Vec(numPregs, UInt(len.W))) 85 val memForRead = Wire(Vec(numPregs, UInt(len.W))) 86 memForRead.zipWithIndex.map{ case(m, i) => 87 if (i == 0) m := mem_0 88 else m := mem(i) 89 } 90 require(Seq(1, 2, 4).contains(bankNum), "bankNum must be 1 or 2 or 4") 91 for (r <- io.readPorts) { 92 if (bankNum == 1) { 93 r.data := memForRead(RegNext(r.addr)) 94 } 95 else { 96 val banks = (0 until bankNum).map { case i => 97 memForRead.zipWithIndex.filter{ case (m, index) => (index % bankNum) == i }.map(_._1) 98 } 99 val bankWidth = bankNum.U.getWidth - 1 100 val hitBankWire = VecInit((0 until bankNum).map { case i => r.addr(bankWidth - 1, 0) === i.U }) 101 val hitBankReg = Reg(Vec(bankNum, Bool())) 102 hitBankReg := hitBankWire 103 val banksRdata = Wire(Vec(bankNum, UInt(len.W))) 104 for (i <- 0 until bankNum) { 105 banksRdata(i) := RegEnable(VecInit(banks(i))(r.addr(r.addr.getWidth - 1, bankWidth)), hitBankWire(i)) 106 } 107 r.data := Mux1H(hitBankReg, banksRdata) 108 } 109 } 110 val writePorts = io.writePorts 111 for (i <- writePorts.indices) { 112 if (i < writePorts.size-1) { 113 val hasSameWrite = writePorts.drop(i + 1).map(w => w.wen && w.addr === writePorts(i).addr && writePorts(i).wen).reduce(_ || _) 114 assert(!hasSameWrite, "RegFile two or more writePorts write same addr") 115 } 116 } 117 for (i <- mem.indices) { 118 if (hasZero && i == 0) { 119 mem_0 := 0.U 120 } 121 else { 122 val wenOH = VecInit(io.writePorts.map(w => w.wen && w.addr === i.U)) 123 val wData = Mux1H(wenOH, io.writePorts.map(_.data)) 124 when(wenOH.asUInt.orR) { 125 if (i == 0) mem_0 := wData 126 else mem(i) := wData 127 } 128 } 129 } 130 131 for (rport <- io.debug_rports) { 132 rport.data := memForRead(rport.addr) 133 } 134} 135 136object Regfile { 137 // non-return version 138 def apply( 139 name : String, 140 numEntries : Int, 141 raddr : Seq[UInt], 142 rdata : Vec[UInt], 143 wen : Seq[Bool], 144 waddr : Seq[UInt], 145 wdata : Seq[UInt], 146 hasZero : Boolean, 147 withReset : Boolean = false, 148 bankNum : Int = 1, 149 debugReadAddr: Option[Seq[UInt]], 150 debugReadData: Option[Vec[UInt]], 151 isVlRegfile : Boolean = false, 152 )(implicit p: Parameters): Unit = { 153 val numReadPorts = raddr.length 154 val numWritePorts = wen.length 155 require(wen.length == waddr.length) 156 require(wen.length == wdata.length) 157 val dataBits = wdata.map(_.getWidth).min 158 require(wdata.map(_.getWidth).min == wdata.map(_.getWidth).max, s"dataBits != $dataBits") 159 val addrBits = waddr.map(_.getWidth).min 160 require(waddr.map(_.getWidth).min == waddr.map(_.getWidth).max, s"addrBits != $addrBits") 161 162 val instanceName = name(0).toLower.toString() + name.drop(1) 163 require(instanceName != name, "Regfile Instance Name can't be same as Module name") 164 val regfile = Module(new Regfile(name, numEntries, numReadPorts, numWritePorts, hasZero, dataBits, addrBits, bankNum, isVlRegfile)).suggestName(instanceName) 165 rdata := regfile.io.readPorts.zip(raddr).map { case (rport, addr) => 166 rport.addr := addr 167 rport.data 168 } 169 170 regfile.io.writePorts.zip(wen).zip(waddr).zip(wdata).foreach{ case (((wport, en), addr), data) => 171 wport.wen := en 172 wport.addr := addr 173 wport.data := data 174 } 175 if (withReset) { 176 val numResetCycles = math.ceil(numEntries / numWritePorts).toInt 177 val resetCounter = RegInit(numResetCycles.U) 178 val resetWaddr = RegInit(VecInit((0 until numWritePorts).map(_.U(log2Up(numEntries + 1).W)))) 179 val inReset = resetCounter =/= 0.U 180 when (inReset) { 181 resetCounter := resetCounter - 1.U 182 resetWaddr := VecInit(resetWaddr.map(_ + numWritePorts.U)) 183 } 184 when (!inReset) { 185 resetWaddr.map(_ := 0.U) 186 } 187 for ((wport, i) <- regfile.io.writePorts.zipWithIndex) { 188 wport.wen := inReset || wen(i) 189 wport.addr := Mux(inReset, resetWaddr(i), waddr(i)) 190 wport.data := wdata(i) 191 } 192 } 193 194 require(debugReadAddr.nonEmpty == debugReadData.nonEmpty, "Both debug addr and data bundles should be empty or not") 195 regfile.io.debug_rports := DontCare 196 if (debugReadAddr.nonEmpty && debugReadData.nonEmpty) { 197 debugReadData.get := VecInit(regfile.io.debug_rports.zip(debugReadAddr.get).map { case (rport, addr) => 198 rport.addr := addr 199 rport.data 200 }) 201 } 202 } 203} 204 205object IntRegFile { 206 // non-return version 207 def apply( 208 name : String, 209 numEntries : Int, 210 raddr : Seq[UInt], 211 rdata : Vec[UInt], 212 wen : Seq[Bool], 213 waddr : Seq[UInt], 214 wdata : Seq[UInt], 215 debugReadAddr: Option[Seq[UInt]], 216 debugReadData: Option[Vec[UInt]], 217 withReset : Boolean = false, 218 bankNum : Int, 219 )(implicit p: Parameters): Unit = { 220 Regfile( 221 name, numEntries, raddr, rdata, wen, waddr, wdata, 222 hasZero = true, withReset, bankNum, debugReadAddr, debugReadData) 223 } 224} 225 226object FpRegFile { 227 // non-return version 228 def apply( 229 name : String, 230 numEntries : Int, 231 raddr : Seq[UInt], 232 rdata : Vec[UInt], 233 wen : Seq[Bool], 234 waddr : Seq[UInt], 235 wdata : Seq[UInt], 236 debugReadAddr: Option[Seq[UInt]], 237 debugReadData: Option[Vec[UInt]], 238 withReset : Boolean = false, 239 bankNum : Int, 240 isVlRegfile : Boolean = false, 241 )(implicit p: Parameters): Unit = { 242 Regfile( 243 name, numEntries, raddr, rdata, wen, waddr, wdata, 244 hasZero = false, withReset, bankNum, debugReadAddr, debugReadData, isVlRegfile) 245 } 246} 247 248object VfRegFile { 249 // non-return version 250 def apply( 251 name : String, 252 numEntries : Int, 253 splitNum : Int, 254 raddr : Seq[UInt], 255 rdata : Vec[UInt], 256 wen : Seq[Seq[Bool]], 257 waddr : Seq[UInt], 258 wdata : Seq[UInt], 259 debugReadAddr: Option[Seq[UInt]], 260 debugReadData: Option[Vec[UInt]], 261 withReset : Boolean = false, 262 )(implicit p: Parameters): Unit = { 263 require(splitNum >= 1, "splitNum should be no less than 1") 264 require(splitNum == wen.length, "splitNum should be equal to length of wen vec") 265 if (splitNum == 1) { 266 Regfile( 267 name, numEntries, raddr, rdata, wen.head, waddr, wdata, 268 hasZero = false, withReset, bankNum = 1, debugReadAddr, debugReadData) 269 } else { 270 val dataWidth = 64 271 val numReadPorts = raddr.length 272 require(splitNum > 1 && wdata.head.getWidth == dataWidth * splitNum) 273 val wdataVec = Wire(Vec(splitNum, Vec(wdata.length, UInt(dataWidth.W)))) 274 val rdataVec = Wire(Vec(splitNum, Vec(raddr.length, UInt(dataWidth.W)))) 275 val debugRDataVec: Option[Vec[Vec[UInt]]] = debugReadData.map(x => Wire(Vec(splitNum, Vec(x.length, UInt(dataWidth.W))))) 276 for (i <- 0 until splitNum) { 277 wdataVec(i) := wdata.map(_ ((i + 1) * dataWidth - 1, i * dataWidth)) 278 Regfile( 279 name + s"Part${i}", numEntries, raddr, rdataVec(i), wen(i), waddr, wdataVec(i), 280 hasZero = false, withReset, bankNum = 1, debugReadAddr, debugRDataVec.map(_(i)) 281 ) 282 } 283 for (i <- 0 until rdata.length) { 284 rdata(i) := Cat(rdataVec.map(_ (i)).reverse) 285 } 286 if (debugReadData.nonEmpty) { 287 for (i <- 0 until debugReadData.get.length) { 288 debugReadData.get(i) := Cat(debugRDataVec.get.map(_ (i)).reverse) 289 } 290 } 291 } 292 } 293}