xref: /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala (revision 66314a3840e5ebe6cc81ca4725bde95942f67489) 
1package xiangshan.backend.regfile
2
3import chisel3._
4import chisel3.util._
5import chisel3.util.experimental.BoringUtils
6import xiangshan._
7
8class RfReadPort extends XSBundle {
9  val addr = Input(UInt(PhyRegIdxWidth.W))
10  val data = Output(UInt(XLEN.W))
11}
12
13class RfWritePort extends XSBundle {
14  val wen = Input(Bool())
15  val addr = Input(UInt(PhyRegIdxWidth.W))
16  val data = Input(UInt(XLEN.W))
17}
18
19class Regfile
20(
21  numReadPorts: Int,
22  numWirtePorts: Int,
23  hasZero: Boolean
24) extends XSModule {
25  val io = IO(new Bundle() {
26    val readPorts = Vec(numReadPorts, new RfReadPort)
27    val writePorts = Vec(numWirtePorts, new RfWritePort)
28  })
29
30  val mem = Mem(NRPhyRegs, UInt(XLEN.W))
31
32  for(r <- io.readPorts){
33    val addr_reg = RegNext(r.addr)
34    r.data := {if(hasZero) Mux(addr_reg===0.U, 0.U, mem(addr_reg)) else mem(addr_reg)}
35  }
36
37  for(w <- io.writePorts){
38    when(w.wen){
39      mem(w.addr) := w.data
40    }
41  }
42  val debugArchRat = WireInit(VecInit(Seq.fill(32)(0.U(PhyRegIdxWidth.W))))
43  BoringUtils.addSink(debugArchRat, if(hasZero) "DEBUG_INI_ARCH_RAT" else "DEBUG_FP_ARCH_RAT")
44
45  val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map(x => if(hasZero && x._2==0) 0.U else mem(x._1))))
46  BoringUtils.addSource(debugArchReg, if(hasZero) "DEBUG_INT_ARCH_REG" else "DEBUG_FP_ARCH_REG")
47}
48