1package xiangshan.backend.regfile 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan._ 7 8class RfReadPort(len: Int)(implicit p: Parameters) extends XSBundle { 9 val addr = Input(UInt(PhyRegIdxWidth.W)) 10 val data = Output(UInt(len.W)) 11 override def cloneType: RfReadPort.this.type = 12 new RfReadPort(len).asInstanceOf[this.type] 13} 14 15class RfWritePort(len: Int)(implicit p: Parameters) extends XSBundle { 16 val wen = Input(Bool()) 17 val addr = Input(UInt(PhyRegIdxWidth.W)) 18 val data = Input(UInt(len.W)) 19 override def cloneType: RfWritePort.this.type = 20 new RfWritePort(len).asInstanceOf[this.type] 21} 22 23class Regfile 24( 25 numReadPorts: Int, 26 numWirtePorts: Int, 27 hasZero: Boolean, 28 len: Int 29)(implicit p: Parameters) extends XSModule { 30 val io = IO(new Bundle() { 31 val readPorts = Vec(numReadPorts, new RfReadPort(len)) 32 val writePorts = Vec(numWirtePorts, new RfWritePort(len)) 33 val debug_rports = Vec(32, new RfReadPort(len)) 34 }) 35 36 println("Regfile: size:" + NRPhyRegs + " read: " + numReadPorts + "write: " + numWirtePorts) 37 38 val useBlackBox = false 39 if (!useBlackBox) { 40 val mem = Reg(Vec(NRPhyRegs, UInt(len.W))) 41 for (r <- io.readPorts) { 42 val rdata = if (hasZero) Mux(r.addr === 0.U, 0.U, mem(r.addr)) else mem(r.addr) 43 r.data := RegNext(rdata) 44 } 45 for (w <- io.writePorts) { 46 when(w.wen) { 47 mem(w.addr) := w.data 48 } 49 } 50 51 for (rport <- io.debug_rports) { 52 val zero_rdata = Mux(rport.addr === 0.U, 0.U, mem(rport.addr)) 53 rport.data := (if (hasZero) zero_rdata else mem(rport.addr)) 54 } 55 } else { 56 57 val regfile = Module(new regfile_160x64_10w16r_sim) 58 59 regfile.io.clk := this.clock 60 regfile.io.gpr := hasZero.B 61 62 regfile.io.wen0 := io.writePorts(0).wen 63 regfile.io.waddr0 := io.writePorts(0).addr 64 regfile.io.wdata0 := io.writePorts(0).data 65 66 regfile.io.wen1 := io.writePorts(1).wen 67 regfile.io.waddr1 := io.writePorts(1).addr 68 regfile.io.wdata1 := io.writePorts(1).data 69 70 regfile.io.wen2 := io.writePorts(2).wen 71 regfile.io.waddr2 := io.writePorts(2).addr 72 regfile.io.wdata2 := io.writePorts(2).data 73 74 regfile.io.wen3 := io.writePorts(3).wen 75 regfile.io.waddr3 := io.writePorts(3).addr 76 regfile.io.wdata3 := io.writePorts(3).data 77 78 regfile.io.wen4 := io.writePorts(4).wen 79 regfile.io.waddr4 := io.writePorts(4).addr 80 regfile.io.wdata4 := io.writePorts(4).data 81 82 regfile.io.wen5 := io.writePorts(5).wen 83 regfile.io.waddr5 := io.writePorts(5).addr 84 regfile.io.wdata5 := io.writePorts(5).data 85 86 regfile.io.wen6 := io.writePorts(6).wen 87 regfile.io.waddr6 := io.writePorts(6).addr 88 regfile.io.wdata6 := io.writePorts(6).data 89 90 regfile.io.wen7 := io.writePorts(7).wen 91 regfile.io.waddr7 := io.writePorts(7).addr 92 regfile.io.wdata7 := io.writePorts(7).data 93 94 regfile.io.wen8 := false.B //io.writePorts(8).wen 95 regfile.io.waddr8 := DontCare //io.writePorts(8).addr 96 regfile.io.wdata8 := DontCare //io.writePorts(8).data 97 98 regfile.io.wen9 := false.B //io.writePorts(9).wen 99 regfile.io.waddr9 := DontCare //io.writePorts(9).addr 100 regfile.io.wdata9 := DontCare //io.writePorts(9).data 101 102 103 regfile.io.raddr0 := io.readPorts(0).addr 104 regfile.io.raddr1 := io.readPorts(1).addr 105 regfile.io.raddr2 := io.readPorts(2).addr 106 regfile.io.raddr3 := io.readPorts(3).addr 107 regfile.io.raddr4 := io.readPorts(4).addr 108 regfile.io.raddr5 := io.readPorts(5).addr 109 regfile.io.raddr6 := io.readPorts(6).addr 110 regfile.io.raddr7 := io.readPorts(7).addr 111 regfile.io.raddr8 := io.readPorts(8).addr 112 regfile.io.raddr9 := io.readPorts(9).addr 113 regfile.io.raddr10 := io.readPorts(10).addr 114 regfile.io.raddr11 := io.readPorts(11).addr 115 regfile.io.raddr12 := io.readPorts(12).addr 116 regfile.io.raddr13 := io.readPorts(13).addr 117 regfile.io.raddr14 := DontCare //io.readPorts(14).addr 118 regfile.io.raddr15 := DontCare //io.readPorts(15).addr 119 120 io.readPorts(0).data := regfile.io.rdata0 121 io.readPorts(1).data := regfile.io.rdata1 122 io.readPorts(2).data := regfile.io.rdata2 123 io.readPorts(3).data := regfile.io.rdata3 124 io.readPorts(4).data := regfile.io.rdata4 125 io.readPorts(5).data := regfile.io.rdata5 126 io.readPorts(6).data := regfile.io.rdata6 127 io.readPorts(7).data := regfile.io.rdata7 128 io.readPorts(8).data := regfile.io.rdata8 129 io.readPorts(9).data := regfile.io.rdata9 130 io.readPorts(10).data := regfile.io.rdata10 131 io.readPorts(11).data := regfile.io.rdata11 132 io.readPorts(12).data := regfile.io.rdata12 133 io.readPorts(13).data := regfile.io.rdata13 134 135 io.debug_rports := DontCare 136 } 137 138} 139 140class regfile_160x64_10w16r_sim extends BlackBox with HasBlackBoxResource { 141 142 val io = IO(new Bundle{ 143 val clk = Input(Clock()) 144 val gpr = Input(Bool()) 145 146 // write 147 val wen0, wen1, wen2, wen3, wen4, wen5, wen6, wen7, wen8, wen9 = Input(Bool()) 148 val waddr0, waddr1, waddr2, waddr3, waddr4, waddr5, waddr6, waddr7, waddr8, waddr9 = Input(UInt(8.W)) 149 val wdata0, wdata1, wdata2, wdata3, wdata4, wdata5, wdata6, wdata7, wdata8, wdata9 = Input(UInt(64.W)) 150 151 // read 152 val raddr0, raddr1, raddr2, raddr3, raddr4, raddr5, raddr6, raddr7 = Input(UInt(8.W)) 153 val raddr8, raddr9, raddr10, raddr11, raddr12, raddr13, raddr14, raddr15 = Input(UInt(8.W)) 154 val rdata0, rdata1, rdata2, rdata3, rdata4, rdata5, rdata6, rdata7 = Output(UInt(64.W)) 155 val rdata8, rdata9, rdata10, rdata11, rdata12, rdata13, rdata14, rdata15 = Output(UInt(64.W)) 156 }) 157 158 val vsrc = "/vsrc/regfile_160x64_10w16r_sim.v" 159 println(s"Regfile: Using verilog source at: $vsrc") 160 setResource(vsrc) 161 162} 163 164