1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.regfile 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.backend.datapath.DataConfig.{DataConfig, FpData, FpRegSrcDataSet, IntData, IntRegSrcDataSet, VecData, VecRegSrcDataSet, VfRegSrcDataSet} 24import xiangshan.backend.exu.ExeUnitParams 25 26class RfReadPort(dataWidth: Int, addrWidth: Int) extends Bundle { 27 val addr = Input(UInt(addrWidth.W)) 28 val data = Output(UInt(dataWidth.W)) 29} 30 31class RfWritePort(dataWidth: Int, addrWidth: Int) extends Bundle { 32 val wen = Input(Bool()) 33 val addr = Input(UInt(addrWidth.W)) 34 val data = Input(UInt(dataWidth.W)) 35} 36 37class RfReadPortWithConfig(val rfReadDataCfg: DataConfig, addrWidth: Int) extends Bundle { 38 val addr: UInt = Input(UInt(addrWidth.W)) 39 val srcType: UInt = Input(UInt(3.W)) 40 41 def readInt: Boolean = IntRegSrcDataSet.contains(rfReadDataCfg) 42 def readFp : Boolean = FpRegSrcDataSet .contains(rfReadDataCfg) 43 def readVec: Boolean = VecRegSrcDataSet.contains(rfReadDataCfg) 44 def readVf : Boolean = VfRegSrcDataSet .contains(rfReadDataCfg) 45} 46 47class RfWritePortWithConfig(val rfWriteDataCfg: DataConfig, addrWidth: Int) extends Bundle { 48 val wen = Input(Bool()) 49 val addr = Input(UInt(addrWidth.W)) 50 val data = Input(UInt(rfWriteDataCfg.dataWidth.W)) 51 val intWen = Input(Bool()) 52 val fpWen = Input(Bool()) 53 val vecWen = Input(Bool()) 54 def writeInt: Boolean = rfWriteDataCfg.isInstanceOf[IntData] 55 def writeFp : Boolean = rfWriteDataCfg.isInstanceOf[FpData] 56 def writeVec: Boolean = rfWriteDataCfg.isInstanceOf[VecData] 57} 58 59class Regfile 60( 61 name: String, 62 numPregs: Int, 63 numReadPorts: Int, 64 numWritePorts: Int, 65 hasZero: Boolean, 66 len: Int, 67 width: Int, 68) extends Module { 69 val io = IO(new Bundle() { 70 val readPorts = Vec(numReadPorts, new RfReadPort(len, width)) 71 val writePorts = Vec(numWritePorts, new RfWritePort(len, width)) 72 val debug_rports = Vec(65, new RfReadPort(len, width)) 73 }) 74 75 println(name + ": size:" + numPregs + " read: " + numReadPorts + " write: " + numWritePorts) 76 77 val mem = Reg(Vec(numPregs, UInt(len.W))) 78 for (r <- io.readPorts) { 79 r.data := RegNext(mem(r.addr)) 80 } 81 val writePorts = io.writePorts 82 for (i <- writePorts.indices) { 83 if (i < writePorts.size-1) { 84 val hasSameWrite = writePorts.drop(i + 1).map(w => w.wen && w.addr === writePorts(i).addr && writePorts(i).wen).reduce(_ || _) 85 assert(!hasSameWrite, "RegFile two or more writePorts write same addr") 86 } 87 } 88 for (i <- mem.indices) { 89 if (hasZero && i == 0) { 90 mem(i) := 0.U 91 } 92 else { 93 val wenOH = VecInit(io.writePorts.map(w => w.wen && w.addr === i.U)) 94 val wData = Mux1H(wenOH, io.writePorts.map(_.data)) 95 when(wenOH.asUInt.orR) { 96 mem(i) := wData 97 } 98 } 99 } 100 101 for (rport <- io.debug_rports) { 102 val zero_rdata = Mux(rport.addr === 0.U, 0.U, mem(rport.addr)) 103 rport.data := (if (hasZero) zero_rdata else mem(rport.addr)) 104 } 105} 106 107object Regfile { 108 // non-return version 109 def apply( 110 name : String, 111 numEntries : Int, 112 raddr : Seq[UInt], 113 rdata : Vec[UInt], 114 wen : Seq[Bool], 115 waddr : Seq[UInt], 116 wdata : Seq[UInt], 117 hasZero : Boolean, 118 withReset : Boolean = false, 119 debugReadAddr: Option[Seq[UInt]], 120 debugReadData: Option[Vec[UInt]], 121 )(implicit p: Parameters): Unit = { 122 val numReadPorts = raddr.length 123 val numWritePorts = wen.length 124 require(wen.length == waddr.length) 125 require(wen.length == wdata.length) 126 val dataBits = wdata.map(_.getWidth).min 127 require(wdata.map(_.getWidth).min == wdata.map(_.getWidth).max, s"dataBits != $dataBits") 128 val addrBits = waddr.map(_.getWidth).min 129 require(waddr.map(_.getWidth).min == waddr.map(_.getWidth).max, s"addrBits != $addrBits") 130 131 val regfile = Module(new Regfile(name, numEntries, numReadPorts, numWritePorts, hasZero, dataBits, addrBits)) 132 rdata := regfile.io.readPorts.zip(raddr).map { case (rport, addr) => 133 rport.addr := addr 134 rport.data 135 } 136 137 regfile.io.writePorts.zip(wen).zip(waddr).zip(wdata).foreach{ case (((wport, en), addr), data) => 138 wport.wen := en 139 wport.addr := addr 140 wport.data := data 141 } 142 if (withReset) { 143 val numResetCycles = math.ceil(numEntries / numWritePorts).toInt 144 val resetCounter = RegInit(numResetCycles.U) 145 val resetWaddr = RegInit(VecInit((0 until numWritePorts).map(_.U(log2Up(numEntries + 1).W)))) 146 val inReset = resetCounter =/= 0.U 147 when (inReset) { 148 resetCounter := resetCounter - 1.U 149 resetWaddr := VecInit(resetWaddr.map(_ + numWritePorts.U)) 150 } 151 when (!inReset) { 152 resetWaddr.map(_ := 0.U) 153 } 154 for ((wport, i) <- regfile.io.writePorts.zipWithIndex) { 155 wport.wen := inReset || wen(i) 156 wport.addr := Mux(inReset, resetWaddr(i), waddr(i)) 157 wport.data := wdata(i) 158 } 159 } 160 161 require(debugReadAddr.nonEmpty == debugReadData.nonEmpty, "Both debug addr and data bundles should be empty or not") 162 regfile.io.debug_rports := DontCare 163 if (debugReadAddr.nonEmpty && debugReadData.nonEmpty) { 164 debugReadData.get := VecInit(regfile.io.debug_rports.zip(debugReadAddr.get).map { case (rport, addr) => 165 rport.addr := addr 166 rport.data 167 }) 168 } 169 } 170} 171 172object IntRegFile { 173 // non-return version 174 def apply( 175 name : String, 176 numEntries : Int, 177 raddr : Seq[UInt], 178 rdata : Vec[UInt], 179 wen : Seq[Bool], 180 waddr : Seq[UInt], 181 wdata : Seq[UInt], 182 debugReadAddr: Option[Seq[UInt]], 183 debugReadData: Option[Vec[UInt]], 184 withReset : Boolean = false, 185 )(implicit p: Parameters): Unit = { 186 Regfile( 187 name, numEntries, raddr, rdata, wen, waddr, wdata, 188 hasZero = true, withReset, debugReadAddr, debugReadData) 189 } 190} 191 192object VfRegFile { 193 // non-return version 194 def apply( 195 name : String, 196 numEntries : Int, 197 splitNum : Int, 198 raddr : Seq[UInt], 199 rdata : Vec[UInt], 200 wen : Seq[Seq[Bool]], 201 waddr : Seq[UInt], 202 wdata : Seq[UInt], 203 debugReadAddr: Option[Seq[UInt]], 204 debugReadData: Option[Vec[UInt]], 205 withReset : Boolean = false, 206 )(implicit p: Parameters): Unit = { 207 require(splitNum >= 1, "splitNum should be no less than 1") 208 require(splitNum == wen.length, "splitNum should be equal to length of wen vec") 209 if (splitNum == 1) { 210 Regfile( 211 name, numEntries, raddr, rdata, wen.head, waddr, wdata, 212 hasZero = false, withReset, debugReadAddr, debugReadData) 213 } else { 214 val dataWidth = 64 215 val numReadPorts = raddr.length 216 require(splitNum > 1 && wdata.head.getWidth == dataWidth * splitNum) 217 val wdataVec = Wire(Vec(splitNum, Vec(wdata.length, UInt(dataWidth.W)))) 218 val rdataVec = Wire(Vec(splitNum, Vec(raddr.length, UInt(dataWidth.W)))) 219 val debugRDataVec: Option[Vec[Vec[UInt]]] = debugReadData.map(x => Wire(Vec(splitNum, Vec(x.length, UInt(dataWidth.W))))) 220 for (i <- 0 until splitNum) { 221 wdataVec(i) := wdata.map(_ ((i + 1) * dataWidth - 1, i * dataWidth)) 222 Regfile( 223 name + s"Part${i}", numEntries, raddr, rdataVec(i), wen(i), waddr, wdataVec(i), 224 hasZero = false, withReset, debugReadAddr, debugRDataVec.map(_(i)) 225 ) 226 } 227 for (i <- 0 until rdata.length) { 228 rdata(i) := Cat(rdataVec.map(_ (i)).reverse) 229 } 230 if (debugReadData.nonEmpty) { 231 for (i <- 0 until debugReadData.get.length) { 232 debugReadData.get(i) := Cat(debugRDataVec.get.map(_ (i)).reverse) 233 } 234 } 235 } 236 } 237}