1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.regfile 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.exu.ExeUnitParams 25 26class RfReadPort(dataWidth: Int, addrWidth: Int) extends Bundle { 27 val addr = Input(UInt(addrWidth.W)) 28 val data = Output(UInt(dataWidth.W)) 29} 30 31class RfWritePort(dataWidth: Int, addrWidth: Int) extends Bundle { 32 val wen = Input(Bool()) 33 val addr = Input(UInt(addrWidth.W)) 34 val data = Input(UInt(dataWidth.W)) 35} 36 37class RfReadPortWithConfig(val rfReadDataCfg: DataConfig, addrWidth: Int) extends Bundle { 38 val addr: UInt = Input(UInt(addrWidth.W)) 39 val srcType: UInt = Input(UInt(3.W)) 40 41 def readInt: Boolean = IntRegSrcDataSet.contains(rfReadDataCfg) 42 def readFp : Boolean = FpRegSrcDataSet .contains(rfReadDataCfg) 43 def readVec: Boolean = VecRegSrcDataSet.contains(rfReadDataCfg) 44 def readVf : Boolean = VecRegSrcDataSet .contains(rfReadDataCfg) 45} 46 47class RfWritePortWithConfig(val rfWriteDataCfg: DataConfig, addrWidth: Int) extends Bundle { 48 val wen = Input(Bool()) 49 val addr = Input(UInt(addrWidth.W)) 50 val data = Input(UInt(rfWriteDataCfg.dataWidth.W)) 51 val intWen = Input(Bool()) 52 val fpWen = Input(Bool()) 53 val vecWen = Input(Bool()) 54 val v0Wen = Input(Bool()) 55 val vlWen = Input(Bool()) 56 def writeInt: Boolean = rfWriteDataCfg.isInstanceOf[IntData] 57 def writeFp : Boolean = rfWriteDataCfg.isInstanceOf[FpData] 58 def writeVec: Boolean = rfWriteDataCfg.isInstanceOf[VecData] 59 def writeV0 : Boolean = rfWriteDataCfg.isInstanceOf[V0Data] 60 def writeVl : Boolean = rfWriteDataCfg.isInstanceOf[VlData] 61} 62 63class Regfile 64( 65 name: String, 66 numPregs: Int, 67 numReadPorts: Int, 68 numWritePorts: Int, 69 hasZero: Boolean, 70 len: Int, 71 width: Int, 72 bankNum: Int = 1, 73) extends Module { 74 val io = IO(new Bundle() { 75 val readPorts = Vec(numReadPorts, new RfReadPort(len, width)) 76 val writePorts = Vec(numWritePorts, new RfWritePort(len, width)) 77 val debug_rports = Vec(65, new RfReadPort(len, width)) 78 }) 79 80 println(name + ": size:" + numPregs + " read: " + numReadPorts + " write: " + numWritePorts) 81 82 val mem = Reg(Vec(numPregs, UInt(len.W))) 83 require(Seq(1, 2, 4).contains(bankNum), "bankNum must be 1 or 2 or 4") 84 for (r <- io.readPorts) { 85 if (bankNum == 1) { 86 r.data := mem(RegNext(r.addr)) 87 } 88 else { 89 val banks = (0 until bankNum).map { case i => 90 mem.zipWithIndex.filter{ case (m, index) => (index % bankNum) == i }.map(_._1) 91 } 92 val bankWidth = bankNum.U.getWidth - 1 93 val hitBankWire = VecInit((0 until bankNum).map { case i => r.addr(bankWidth - 1, 0) === i.U }) 94 val hitBankReg = Reg(Vec(bankNum, Bool())) 95 hitBankReg := hitBankWire 96 val banksRdata = Wire(Vec(bankNum, UInt(len.W))) 97 for (i <- 0 until bankNum) { 98 banksRdata(i) := RegEnable(VecInit(banks(i))(r.addr(r.addr.getWidth - 1, bankWidth)), hitBankWire(i)) 99 } 100 r.data := Mux1H(hitBankReg, banksRdata) 101 } 102 } 103 val writePorts = io.writePorts 104 for (i <- writePorts.indices) { 105 if (i < writePorts.size-1) { 106 val hasSameWrite = writePorts.drop(i + 1).map(w => w.wen && w.addr === writePorts(i).addr && writePorts(i).wen).reduce(_ || _) 107 assert(!hasSameWrite, "RegFile two or more writePorts write same addr") 108 } 109 } 110 for (i <- mem.indices) { 111 if (hasZero && i == 0) { 112 mem(i) := 0.U 113 } 114 else { 115 val wenOH = VecInit(io.writePorts.map(w => w.wen && w.addr === i.U)) 116 val wData = Mux1H(wenOH, io.writePorts.map(_.data)) 117 when(wenOH.asUInt.orR) { 118 mem(i) := wData 119 } 120 } 121 } 122 123 for (rport <- io.debug_rports) { 124 val zero_rdata = Mux(rport.addr === 0.U, 0.U, mem(rport.addr)) 125 rport.data := (if (hasZero) zero_rdata else mem(rport.addr)) 126 } 127} 128 129object Regfile { 130 // non-return version 131 def apply( 132 name : String, 133 numEntries : Int, 134 raddr : Seq[UInt], 135 rdata : Vec[UInt], 136 wen : Seq[Bool], 137 waddr : Seq[UInt], 138 wdata : Seq[UInt], 139 hasZero : Boolean, 140 withReset : Boolean = false, 141 bankNum : Int = 1, 142 debugReadAddr: Option[Seq[UInt]], 143 debugReadData: Option[Vec[UInt]], 144 )(implicit p: Parameters): Unit = { 145 val numReadPorts = raddr.length 146 val numWritePorts = wen.length 147 require(wen.length == waddr.length) 148 require(wen.length == wdata.length) 149 val dataBits = wdata.map(_.getWidth).min 150 require(wdata.map(_.getWidth).min == wdata.map(_.getWidth).max, s"dataBits != $dataBits") 151 val addrBits = waddr.map(_.getWidth).min 152 require(waddr.map(_.getWidth).min == waddr.map(_.getWidth).max, s"addrBits != $addrBits") 153 154 val regfile = Module(new Regfile(name, numEntries, numReadPorts, numWritePorts, hasZero, dataBits, addrBits, bankNum)) 155 rdata := regfile.io.readPorts.zip(raddr).map { case (rport, addr) => 156 rport.addr := addr 157 rport.data 158 } 159 160 regfile.io.writePorts.zip(wen).zip(waddr).zip(wdata).foreach{ case (((wport, en), addr), data) => 161 wport.wen := en 162 wport.addr := addr 163 wport.data := data 164 } 165 if (withReset) { 166 val numResetCycles = math.ceil(numEntries / numWritePorts).toInt 167 val resetCounter = RegInit(numResetCycles.U) 168 val resetWaddr = RegInit(VecInit((0 until numWritePorts).map(_.U(log2Up(numEntries + 1).W)))) 169 val inReset = resetCounter =/= 0.U 170 when (inReset) { 171 resetCounter := resetCounter - 1.U 172 resetWaddr := VecInit(resetWaddr.map(_ + numWritePorts.U)) 173 } 174 when (!inReset) { 175 resetWaddr.map(_ := 0.U) 176 } 177 for ((wport, i) <- regfile.io.writePorts.zipWithIndex) { 178 wport.wen := inReset || wen(i) 179 wport.addr := Mux(inReset, resetWaddr(i), waddr(i)) 180 wport.data := wdata(i) 181 } 182 } 183 184 require(debugReadAddr.nonEmpty == debugReadData.nonEmpty, "Both debug addr and data bundles should be empty or not") 185 regfile.io.debug_rports := DontCare 186 if (debugReadAddr.nonEmpty && debugReadData.nonEmpty) { 187 debugReadData.get := VecInit(regfile.io.debug_rports.zip(debugReadAddr.get).map { case (rport, addr) => 188 rport.addr := addr 189 rport.data 190 }) 191 } 192 } 193} 194 195object IntRegFile { 196 // non-return version 197 def apply( 198 name : String, 199 numEntries : Int, 200 raddr : Seq[UInt], 201 rdata : Vec[UInt], 202 wen : Seq[Bool], 203 waddr : Seq[UInt], 204 wdata : Seq[UInt], 205 debugReadAddr: Option[Seq[UInt]], 206 debugReadData: Option[Vec[UInt]], 207 withReset : Boolean = false, 208 bankNum : Int, 209 )(implicit p: Parameters): Unit = { 210 Regfile( 211 name, numEntries, raddr, rdata, wen, waddr, wdata, 212 hasZero = true, withReset, bankNum, debugReadAddr, debugReadData) 213 } 214} 215 216object FpRegFile { 217 // non-return version 218 def apply( 219 name : String, 220 numEntries : Int, 221 raddr : Seq[UInt], 222 rdata : Vec[UInt], 223 wen : Seq[Bool], 224 waddr : Seq[UInt], 225 wdata : Seq[UInt], 226 debugReadAddr: Option[Seq[UInt]], 227 debugReadData: Option[Vec[UInt]], 228 withReset : Boolean = false, 229 bankNum : Int, 230 )(implicit p: Parameters): Unit = { 231 Regfile( 232 name, numEntries, raddr, rdata, wen, waddr, wdata, 233 hasZero = false, withReset, bankNum, debugReadAddr, debugReadData) 234 } 235} 236 237object VfRegFile { 238 // non-return version 239 def apply( 240 name : String, 241 numEntries : Int, 242 splitNum : Int, 243 raddr : Seq[UInt], 244 rdata : Vec[UInt], 245 wen : Seq[Seq[Bool]], 246 waddr : Seq[UInt], 247 wdata : Seq[UInt], 248 debugReadAddr: Option[Seq[UInt]], 249 debugReadData: Option[Vec[UInt]], 250 withReset : Boolean = false, 251 )(implicit p: Parameters): Unit = { 252 require(splitNum >= 1, "splitNum should be no less than 1") 253 require(splitNum == wen.length, "splitNum should be equal to length of wen vec") 254 if (splitNum == 1) { 255 Regfile( 256 name, numEntries, raddr, rdata, wen.head, waddr, wdata, 257 hasZero = false, withReset, bankNum = 1, debugReadAddr, debugReadData) 258 } else { 259 val dataWidth = 64 260 val numReadPorts = raddr.length 261 require(splitNum > 1 && wdata.head.getWidth == dataWidth * splitNum) 262 val wdataVec = Wire(Vec(splitNum, Vec(wdata.length, UInt(dataWidth.W)))) 263 val rdataVec = Wire(Vec(splitNum, Vec(raddr.length, UInt(dataWidth.W)))) 264 val debugRDataVec: Option[Vec[Vec[UInt]]] = debugReadData.map(x => Wire(Vec(splitNum, Vec(x.length, UInt(dataWidth.W))))) 265 for (i <- 0 until splitNum) { 266 wdataVec(i) := wdata.map(_ ((i + 1) * dataWidth - 1, i * dataWidth)) 267 Regfile( 268 name + s"Part${i}", numEntries, raddr, rdataVec(i), wen(i), waddr, wdataVec(i), 269 hasZero = false, withReset, bankNum = 1, debugReadAddr, debugRDataVec.map(_(i)) 270 ) 271 } 272 for (i <- 0 until rdata.length) { 273 rdata(i) := Cat(rdataVec.map(_ (i)).reverse) 274 } 275 if (debugReadData.nonEmpty) { 276 for (i <- 0 until debugReadData.get.length) { 277 debugReadData.get(i) := Cat(debugRDataVec.get.map(_ (i)).reverse) 278 } 279 } 280 } 281 } 282}