1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan._ 7import utils._ 8 9class WakeupQueue(number: Int)(implicit p: Parameters) extends XSModule { 10 val io = IO(new Bundle { 11 val in = Flipped(ValidIO(new MicroOp)) 12 val out = ValidIO(new MicroOp) 13 val redirect = Flipped(ValidIO(new Redirect)) 14 val flush = Input(Bool()) 15 }) 16 if (number < 0) { 17 io.out.valid := false.B 18 io.out.bits := DontCare 19 } else if(number == 0) { 20 io.in <> io.out 21 io.out.valid := io.in.valid 22 // NOTE: no delay bypass don't care redirect 23 } else { 24 val queue = Seq.fill(number)(RegInit(0.U.asTypeOf(new Bundle{ 25 val valid = Bool() 26 val bits = new MicroOp 27 }))) 28 queue(0).valid := io.in.valid && !io.in.bits.roqIdx.needFlush(io.redirect, io.flush) 29 queue(0).bits := io.in.bits 30 (0 until (number-1)).map{i => 31 queue(i+1) := queue(i) 32 queue(i+1).valid := queue(i).valid && !queue(i).bits.roqIdx.needFlush(io.redirect, io.flush) 33 } 34 io.out.valid := queue(number-1).valid 35 io.out.bits := queue(number-1).bits 36 for (i <- 0 until number) { 37 XSDebug(queue(i).valid, p"BPQue(${i.U}): pc:${Hexadecimal(queue(i).bits.cf.pc)} roqIdx:${queue(i).bits.roqIdx}" + 38 p" pdest:${queue(i).bits.pdest} rfWen:${queue(i).bits.ctrl.rfWen} fpWen${queue(i).bits.ctrl.fpWen}\n") 39 } 40 } 41} 42