1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles 9import xiangshan.backend.datapath.DataConfig.VAddrData 10import xiangshan.backend.regfile.RfWritePortWithConfig 11import xiangshan.backend.rename.BusyTable 12import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 13import xiangshan.backend.Bundles.{DynInst, IssueQueueWakeUpBundle} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numIntWb 24 val numVfStateWrite = backendParams.numVfWb 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 // params alias 39 private val LoadQueueSize = VirtualLoadQueueSize 40 41 val fromTop = new Bundle { 42 val hartId = Input(UInt(8.W)) 43 } 44 val fromWbFuBusyTable = new Bundle{ 45 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 46 } 47 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 48 49 val fromCtrlBlock = new Bundle { 50 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 51 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 52 val flush = Flipped(ValidIO(new Redirect)) 53 } 54 val fromDispatch = new Bundle { 55 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 56 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 57 } 58 val intWriteBack = MixedVec(Vec(backendParams.intPregParams.numWrite, 59 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 60 val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite, 61 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 62 val toDataPath: MixedVec[MixedVec[DecoupledIO[Bundles.IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 63 val fromDataPath: MixedVec[MixedVec[Bundles.OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 64 65 val memIO = if (params.isMemSchd) Some(new Bundle { 66 val lsqEnqIO = Flipped(new LsqEnqIO) 67 }) else None 68 val fromMem = if (params.isMemSchd) Some(new Bundle { 69 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 70 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 71 val stIssuePtr = Input(new SqPtr()) 72 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 73 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 74 // from lsq 75 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 76 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 77 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 78 }) else None 79 val toMem = if (params.isMemSchd) Some(new Bundle { 80 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 81 }) else None 82} 83 84abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 85 extends LazyModuleImp(wrapper) 86 with HasXSParameter 87{ 88 val io = IO(new SchedulerIO()) 89 90 // alias 91 private val schdType = params.schdType 92 private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0)) 93 private val numPregs = params.numPregs 94 95 // Modules 96 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 97 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 98 99 // BusyTable Modules 100 val intBusyTable = schdType match { 101 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite))) 102 case _ => None 103 } 104 105 val vfBusyTable = schdType match { 106 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite))) 107 case _ => None 108 } 109 110 dispatch2Iq.io match { case dp2iq => 111 dp2iq.redirect <> io.fromCtrlBlock.flush 112 dp2iq.in <> io.fromDispatch.uops 113 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 114 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 115 } 116 117 intBusyTable match { 118 case Some(bt) => 119 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 120 btAllocPregs.valid := dpAllocPregs.isInt 121 btAllocPregs.bits := dpAllocPregs.preg 122 } 123 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 124 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 125 wb.bits := io.intWriteBack(i).addr 126 } 127 case None => 128 } 129 130 vfBusyTable match { 131 case Some(bt) => 132 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 133 btAllocPregs.valid := dpAllocPregs.isFp 134 btAllocPregs.bits := dpAllocPregs.preg 135 } 136 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 137 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 138 wb.bits := io.vfWriteBack(i).addr 139 } 140 case None => 141 } 142 143 val wakeupFromWBVec = Wire(Vec(params.numWakeupFromWB, ValidIO(new IssueQueueWakeUpBundle(params.pregIdxWidth)))) 144 val writeback = params.schdType match { 145 case IntScheduler() => io.intWriteBack 146 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 147 case VfScheduler() => io.vfWriteBack 148 case _ => Seq() 149 } 150 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 151 sink.valid := source.wen 152 sink.bits.rfWen := source.intWen 153 sink.bits.fpWen := source.fpWen 154 sink.bits.vecWen := source.vecWen 155 sink.bits.pdest := source.addr 156 } 157 158 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 159 toDp <> issueQueues(i).io.deq 160 } 161} 162 163class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 164 extends SchedulerImpBase(wrapper) 165 with HasXSParameter 166{ 167// dontTouch(io.vfWbFuBusyTable) 168 println(s"[SchedulerArithImp] " + 169 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 170 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 171 172 issueQueues.zipWithIndex.foreach { case (iq, i) => 173 iq.io.flush <> io.fromCtrlBlock.flush 174 iq.io.enq <> dispatch2Iq.io.out(i) 175 iq.io.wakeup := wakeupFromWBVec 176 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 177 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 178 deqResp.bits.respType := RSFeedbackType.issueSuccess 179 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 180 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 181 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 182 183 } 184 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 185 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 186 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 187 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 188 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 189 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 190 191 } 192 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 193 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 194 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 195 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 196 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 197 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 198 199 } 200 201 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 202 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 203 } 204 205 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 206 case imp: IssueQueueIntImp => imp.io.enqJmp 207 case _ => None 208 }.filter(_.nonEmpty).flatMap(_.get) 209 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 210 211 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 212 iqJmp.pc := pc 213 iqJmp.target := target 214 } 215} 216 217class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 218 extends SchedulerImpBase(wrapper) 219 with HasXSParameter 220{ 221 println(s"[SchedulerMemImp] " + 222 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 223 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 224 225 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 226 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 227 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 228 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 229 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 230 231 issueQueues.zipWithIndex.foreach { case (iq, i) => 232 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 233 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 234 deqResp.bits.respType := RSFeedbackType.issueSuccess 235 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 236 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 237 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 238 239 } 240 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 241 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 242 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 243 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 244 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 245 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 246 247 } 248 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 249 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 250 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 251 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 252 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 253 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 254 255 } 256 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 257 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 258 } 259 260 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 261 iq.io.flush <> io.fromCtrlBlock.flush 262 iq.io.enq <> dispatch2Iq.io.out(i) 263 iq.io.wakeup := wakeupFromWBVec 264 } 265 266 ldAddrIQs.foreach { 267 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 268 case _ => 269 } 270 271 stAddrIQs.foreach { 272 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 273 case _ => 274 } 275 276 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 277 278 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 279 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 280 val isAllReady = staIQ.ready && stdIQ.ready 281 di.ready := isAllReady 282 staIQ.valid := di.valid && isAllReady 283 stdIQ.valid := di.valid && isAllReady 284 } 285 } 286 287 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 288 s"should be equal to number of data IQs(${stDataIQs})") 289 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 290 stdIQ.io.flush <> io.fromCtrlBlock.flush 291 292 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 293 stdIQEnq.bits := staIQEnq.bits 294 // Store data reuses store addr src(1) in dispatch2iq 295 // [dispatch2iq] --src*------src*(0)--> [staIQ] 296 // \ 297 // ---src*(1)--> [stdIQ] 298 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 299 // instead of dispatch2Iq.io.out(x).bits.src*(1) 300 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 301 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 302 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 303 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 304 } 305 stdIQ.io.wakeup := wakeupFromWBVec 306 } 307 308 val lsqEnqCtrl = Module(new LsqEnqCtrl) 309 310 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 311 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 312 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 313 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 314 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 315 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 316 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 317} 318