1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.regfile.RfWritePortWithConfig 13import xiangshan.backend.rename.BusyTable 14import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 15 16sealed trait SchedulerType 17 18case class IntScheduler() extends SchedulerType 19case class MemScheduler() extends SchedulerType 20case class VfScheduler() extends SchedulerType 21case class NoScheduler() extends SchedulerType 22 23class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 24 override def shouldBeInlined: Boolean = false 25 26 val numIntStateWrite = backendParams.numPregWb(IntData()) 27 val numVfStateWrite = backendParams.numPregWb(VecData()) 28 29 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 30 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 31 32 lazy val module: SchedulerImpBase = params.schdType match { 33 case IntScheduler() => new SchedulerArithImp(this)(params, p) 34 case MemScheduler() => new SchedulerMemImp(this)(params, p) 35 case VfScheduler() => new SchedulerArithImp(this)(params, p) 36 case _ => null 37 } 38} 39 40class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 41 // params alias 42 private val LoadQueueSize = VirtualLoadQueueSize 43 44 val fromTop = new Bundle { 45 val hartId = Input(UInt(8.W)) 46 } 47 val fromWbFuBusyTable = new Bundle{ 48 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 49 } 50 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 51 52 val fromCtrlBlock = new Bundle { 53 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 54 val flush = Flipped(ValidIO(new Redirect)) 55 } 56 val fromDispatch = new Bundle { 57 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 58 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 59 } 60 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 61 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 62 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 63 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 64 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 65 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 66 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 67 68 val fromSchedulers = new Bundle { 69 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 70 } 71 72 val toSchedulers = new Bundle { 73 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 74 } 75 76 val fromDataPath = new Bundle { 77 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 78 val og0Cancel = Input(ExuOH(backendParams.numExu)) 79 // Todo: remove this after no cancel signal from og1 80 val og1Cancel = Input(ExuOH(backendParams.numExu)) 81 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 82 // just be compatible to old code 83 def apply(i: Int)(j: Int) = resp(i)(j) 84 } 85 86 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 87 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 88 89 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 90 91 val memIO = if (params.isMemSchd) Some(new Bundle { 92 val lsqEnqIO = Flipped(new LsqEnqIO) 93 }) else None 94 val fromMem = if (params.isMemSchd) Some(new Bundle { 95 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 96 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 97 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 98 val stIssuePtr = Input(new SqPtr()) 99 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 100 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 101 // from lsq 102 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 103 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 104 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 105 }) else None 106 val toMem = if (params.isMemSchd) Some(new Bundle { 107 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 108 }) else None 109} 110 111abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 112 extends LazyModuleImp(wrapper) 113 with HasXSParameter 114{ 115 val io = IO(new SchedulerIO()) 116 117 // alias 118 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 119 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 120 private val schdType = params.schdType 121 122 // Modules 123 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 124 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 125 126 // BusyTable Modules 127 val intBusyTable = schdType match { 128 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 129 case _ => None 130 } 131 132 val vfBusyTable = schdType match { 133 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 134 case _ => None 135 } 136 137 dispatch2Iq.io match { case dp2iq => 138 dp2iq.redirect <> io.fromCtrlBlock.flush 139 dp2iq.in <> io.fromDispatch.uops 140 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 141 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 142 } 143 144 intBusyTable match { 145 case Some(bt) => 146 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 147 btAllocPregs.valid := dpAllocPregs.isInt 148 btAllocPregs.bits := dpAllocPregs.preg 149 } 150 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 151 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 152 wb.bits := io.intWriteBack(i).addr 153 } 154 bt.io.wakeUp := io.fromSchedulers.wakeupVec 155 bt.io.cancel := io.fromDataPath.cancelToBusyTable 156 case None => 157 } 158 159 vfBusyTable match { 160 case Some(bt) => 161 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 162 btAllocPregs.valid := dpAllocPregs.isFp 163 btAllocPregs.bits := dpAllocPregs.preg 164 } 165 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 166 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 167 wb.bits := io.vfWriteBack(i).addr 168 } 169 bt.io.wakeUp := io.fromSchedulers.wakeupVec 170 bt.io.cancel := io.fromDataPath.cancelToBusyTable 171 case None => 172 } 173 174 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 175 val writeback = params.schdType match { 176 case IntScheduler() => io.intWriteBack 177 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 178 case VfScheduler() => io.vfWriteBack 179 case _ => Seq() 180 } 181 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 182 sink.valid := source.wen 183 sink.bits.rfWen := source.intWen 184 sink.bits.fpWen := source.fpWen 185 sink.bits.vecWen := source.vecWen 186 sink.bits.pdest := source.addr 187 } 188 189 // Connect bundles having the same wakeup source 190 issueQueues.zipWithIndex.foreach { case(iq, i) => 191 iq.io.wakeupFromIQ.foreach { wakeUp => 192 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 193 } 194 iq.io.og0Cancel := io.fromDataPath.og0Cancel 195 iq.io.og1Cancel := io.fromDataPath.og1Cancel 196 iq.io.ldCancel := io.ldCancel 197 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 198 } 199 200 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 201 issueQueues.flatMap(_.io.wakeupToIQ) 202 .map(x => (x.bits.exuIdx, x)) 203 .toMap 204 205 // Connect bundles having the same wakeup source 206 io.toSchedulers.wakeupVec.foreach { wakeUp => 207 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 208 } 209 210 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 211 toDp <> issueQueues(i).io.deq 212 } 213 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 214 toDpDy <> issueQueues(i).io.deqDelay 215 } 216 217 // Response 218 issueQueues.zipWithIndex.foreach { case (iq, i) => 219 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 220 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 221 deqResp.bits.respType := RSFeedbackType.issueSuccess 222 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 223 deqResp.bits.dataInvalidSqIdx := DontCare 224 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 225 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 226 } 227 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 228 og0Resp := io.fromDataPath(i)(j).og0resp 229 } 230 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 231 og1Resp := io.fromDataPath(i)(j).og1resp 232 } 233 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 234 finalIssueResp := io.loadFinalIssueResp(i)(j) 235 }) 236 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 237 memAddrIssueResp := io.memAddrIssueResp(i)(j) 238 }) 239 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 240 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 241 } 242 243 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 244 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 245 246 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 247 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 248} 249 250class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 251 extends SchedulerImpBase(wrapper) 252 with HasXSParameter 253{ 254// dontTouch(io.vfWbFuBusyTable) 255 println(s"[SchedulerArithImp] " + 256 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 257 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 258 259 issueQueues.zipWithIndex.foreach { case (iq, i) => 260 iq.io.flush <> io.fromCtrlBlock.flush 261 iq.io.enq <> dispatch2Iq.io.out(i) 262 iq.io.wakeupFromWB := wakeupFromWBVec 263 } 264} 265 266// FIXME: Vector mem instructions may not be handled properly! 267class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 268 extends SchedulerImpBase(wrapper) 269 with HasXSParameter 270{ 271 println(s"[SchedulerMemImp] " + 272 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 273 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 274 275 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 276 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 277 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 278 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 279 val hyuIQs = issueQueues.filter(iq => iq.params.HyuCnt > 0) 280 281 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 282 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 283 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 284 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 285 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 286 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 287 288 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 289 290 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 291 iq.io.flush <> io.fromCtrlBlock.flush 292 iq.io.enq <> dispatch2Iq.io.out(i) 293 iq.io.wakeupFromWB := wakeupFromWBVec 294 } 295 296 ldAddrIQs.foreach { 297 case imp: IssueQueueMemAddrImp => 298 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 299 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 300 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 301 case _ => 302 } 303 304 stAddrIQs.foreach { 305 case imp: IssueQueueMemAddrImp => 306 imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 307 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 308 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 309 case _ => 310 } 311 312 hyuIQs.foreach { 313 case imp: IssueQueueMemAddrImp => 314 imp.io.memIO.get.feedbackIO <> io.fromMem.get.hyuFeedback 315 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 316 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 317 case _ => 318 } 319 320 // TODO: Implement vstu 321 issueQueues.filter(iq => iq.params.VstuCnt > 0).foreach { 322 case imp: IssueQueueMemAddrImp => 323 imp.io.memIO.get.feedbackIO <> DontCare 324 imp.io.memIO.get.checkWait.stIssuePtr := DontCare 325 imp.io.memIO.get.checkWait.memWaitUpdateReq := DontCare 326 case _ => 327 } 328 329 // TODO: Implement vldu 330 issueQueues.filter(iq => iq.params.VlduCnt > 0).foreach { 331 case imp: IssueQueueMemAddrImp => 332 imp.io.memIO.get.feedbackIO <> DontCare 333 imp.io.memIO.get.checkWait.stIssuePtr := DontCare 334 imp.io.memIO.get.checkWait.memWaitUpdateReq := DontCare 335 case _ => 336 } 337 338 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 339 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 340 341 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 342 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 343 344 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 345 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 346 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 347 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 348 349 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 350 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 351 352 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 353 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 354 355 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 356 dispatch2Iq.io.out(idxInSchBlk).zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 357 val isAllReady = staIQ.ready && stdIQ.ready 358 dp.ready := isAllReady 359 staIQ.valid := dp.valid && isAllReady 360 stdIQ.valid := dp.valid && isAllReady 361 } 362 } 363 364 for ((idxInSchBlk, i) <- hyaIdxSeq.zipWithIndex) { 365 dispatch2Iq.io.out(idxInSchBlk).zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 366 val isAllReady = hyaIQ.ready && hydIQ.ready 367 dp.ready := isAllReady 368 hyaIQ.valid := dp.valid && isAllReady 369 hydIQ.valid := dp.valid && isAllReady && FuType.isStore(dp.bits.fuType) 370 } 371 } 372 373 stDataIQs.zipWithIndex.foreach { case (iq, i) => 374 iq.io.flush <> io.fromCtrlBlock.flush 375 iq.io.wakeupFromWB := wakeupFromWBVec 376 } 377 378 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 379 stdIQEnq.bits := staIQEnq.bits 380 // Store data reuses store addr src(1) in dispatch2iq 381 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 382 // \ 383 // ---src*(1)--> [stdIQ] 384 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 385 // instead of dispatch2Iq.io.out(x).bits.src*(1) 386 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 387 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 388 stdIQEnq.bits.dataSource(0) := staIQEnq.bits.dataSource(1) 389 stdIQEnq.bits.l1ExuOH(0) := staIQEnq.bits.l1ExuOH(1) 390 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 391 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 392 } 393 394 val lsqEnqCtrl = Module(new LsqEnqCtrl) 395 396 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 397 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 398 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 399 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 400 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 401 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 402 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 403} 404