1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles 9import xiangshan.backend.datapath.DataConfig.VAddrData 10import xiangshan.backend.regfile.RfWritePortWithConfig 11import xiangshan.backend.rename.BusyTable 12import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 13import xiangshan.backend.Bundles.{DynInst, IssueQueueCancelBundle, IssueQueueIQWakeUpBundle, IssueQueueWBWakeUpBundle} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numIntWb 24 val numVfStateWrite = backendParams.numVfWb 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 // params alias 39 private val LoadQueueSize = VirtualLoadQueueSize 40 41 val fromTop = new Bundle { 42 val hartId = Input(UInt(8.W)) 43 } 44 val fromWbFuBusyTable = new Bundle{ 45 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 46 } 47 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 48 49 val fromCtrlBlock = new Bundle { 50 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 51 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 52 val flush = Flipped(ValidIO(new Redirect)) 53 } 54 val fromDispatch = new Bundle { 55 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 56 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 57 } 58 val intWriteBack = MixedVec(Vec(backendParams.intPregParams.numWrite, 59 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 60 val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite, 61 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 62 val toDataPath: MixedVec[MixedVec[DecoupledIO[Bundles.IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 63 64 val fromSchedulers = new Bundle { 65 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 66 } 67 68 val toSchedulers = new Bundle { 69 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 70 } 71 72 val fromDataPath = new Bundle { 73 val resp: MixedVec[MixedVec[Bundles.OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 74 val cancel: MixedVec[IssueQueueCancelBundle] = Input(MixedVec(params.genCancelBundle(cancelStages))) 75 // just be compatible to old code 76 def apply(i: Int)(j: Int) = resp(i)(j) 77 } 78 79 80 val memIO = if (params.isMemSchd) Some(new Bundle { 81 val lsqEnqIO = Flipped(new LsqEnqIO) 82 }) else None 83 val fromMem = if (params.isMemSchd) Some(new Bundle { 84 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 85 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 86 val stIssuePtr = Input(new SqPtr()) 87 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 88 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 89 // from lsq 90 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 91 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 92 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 93 }) else None 94 val toMem = if (params.isMemSchd) Some(new Bundle { 95 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 96 }) else None 97} 98 99abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 100 extends LazyModuleImp(wrapper) 101 with HasXSParameter 102{ 103 val io = IO(new SchedulerIO()) 104 105 // alias 106 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 107 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 108 private val schdType = params.schdType 109 private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0)) 110 private val numPregs = params.numPregs 111 112 // Modules 113 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 114 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 115 116 // BusyTable Modules 117 val intBusyTable = schdType match { 118 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite))) 119 case _ => None 120 } 121 122 val vfBusyTable = schdType match { 123 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite))) 124 case _ => None 125 } 126 127 dispatch2Iq.io match { case dp2iq => 128 dp2iq.redirect <> io.fromCtrlBlock.flush 129 dp2iq.in <> io.fromDispatch.uops 130 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 131 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 132 } 133 134 intBusyTable match { 135 case Some(bt) => 136 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 137 btAllocPregs.valid := dpAllocPregs.isInt 138 btAllocPregs.bits := dpAllocPregs.preg 139 } 140 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 141 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 142 wb.bits := io.intWriteBack(i).addr 143 } 144 case None => 145 } 146 147 vfBusyTable match { 148 case Some(bt) => 149 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 150 btAllocPregs.valid := dpAllocPregs.isFp 151 btAllocPregs.bits := dpAllocPregs.preg 152 } 153 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 154 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 155 wb.bits := io.vfWriteBack(i).addr 156 } 157 case None => 158 } 159 160 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 161 val writeback = params.schdType match { 162 case IntScheduler() => io.intWriteBack 163 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 164 case VfScheduler() => io.vfWriteBack 165 case _ => Seq() 166 } 167 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 168 sink.valid := source.wen 169 sink.bits.rfWen := source.intWen 170 sink.bits.fpWen := source.fpWen 171 sink.bits.vecWen := source.vecWen 172 sink.bits.pdest := source.addr 173 } 174 175 // Connect bundles having the same wakeup source 176 issueQueues.foreach { iq => 177 iq.io.wakeupFromIQ.foreach { wakeUp => 178 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 179 } 180 iq.io.cancelFromDataPath.map (sink => { 181 sink.cancelVec := io.fromDataPath.cancel.find(_.exuIdx == sink.exuIdx).get.cancelVec 182 }) 183 } 184 185 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 186 issueQueues.flatMap(_.io.wakeupToIQ) 187 .map(x => (x.bits.exuIdx, x)) 188 .toMap 189 190 // Connect bundles having the same wakeup source 191 io.toSchedulers.wakeupVec.foreach { wakeUp => 192 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 193 } 194 195 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 196 toDp <> issueQueues(i).io.deq 197 } 198 199 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 200 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 201 202 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 203 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 204} 205 206class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 207 extends SchedulerImpBase(wrapper) 208 with HasXSParameter 209{ 210// dontTouch(io.vfWbFuBusyTable) 211 println(s"[SchedulerArithImp] " + 212 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 213 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 214 215 issueQueues.zipWithIndex.foreach { case (iq, i) => 216 iq.io.flush <> io.fromCtrlBlock.flush 217 iq.io.enq <> dispatch2Iq.io.out(i) 218 iq.io.wakeupFromWB := wakeupFromWBVec 219 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 220 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 221 deqResp.bits.respType := RSFeedbackType.issueSuccess 222 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 223 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 224 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 225 226 } 227 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 228 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 229 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 230 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 231 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 232 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 233 234 } 235 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 236 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 237 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 238 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 239 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 240 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 241 242 } 243 244 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 245 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 246 } 247 248 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 249 case imp: IssueQueueIntImp => imp.io.enqJmp 250 case _ => None 251 }.filter(_.nonEmpty).flatMap(_.get) 252 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 253 254 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 255 iqJmp.pc := pc 256 iqJmp.target := target 257 } 258} 259 260class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 261 extends SchedulerImpBase(wrapper) 262 with HasXSParameter 263{ 264 println(s"[SchedulerMemImp] " + 265 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 266 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 267 268 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 269 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 270 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 271 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 272 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 273 274 issueQueues.zipWithIndex.foreach { case (iq, i) => 275 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 276 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 277 deqResp.bits.respType := RSFeedbackType.issueSuccess 278 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 279 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 280 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 281 282 } 283 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 284 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 285 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 286 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 287 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 288 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 289 290 } 291 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 292 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 293 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 294 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 295 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 296 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 297 298 } 299 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 300 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 301 } 302 303 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 304 iq.io.flush <> io.fromCtrlBlock.flush 305 iq.io.enq <> dispatch2Iq.io.out(i) 306 iq.io.wakeupFromWB := wakeupFromWBVec 307 } 308 309 ldAddrIQs.foreach { 310 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 311 case _ => 312 } 313 314 stAddrIQs.foreach { 315 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 316 case _ => 317 } 318 319 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 320 321 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 322 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 323 val isAllReady = staIQ.ready && stdIQ.ready 324 di.ready := isAllReady 325 staIQ.valid := di.valid && isAllReady 326 stdIQ.valid := di.valid && isAllReady 327 } 328 } 329 330 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 331 s"should be equal to number of data IQs(${stDataIQs})") 332 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 333 stdIQ.io.flush <> io.fromCtrlBlock.flush 334 335 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 336 stdIQEnq.bits := staIQEnq.bits 337 // Store data reuses store addr src(1) in dispatch2iq 338 // [dispatch2iq] --src*------src*(0)--> [staIQ] 339 // \ 340 // ---src*(1)--> [stdIQ] 341 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 342 // instead of dispatch2Iq.io.out(x).bits.src*(1) 343 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 344 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 345 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 346 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 347 } 348 stdIQ.io.wakeupFromWB := wakeupFromWBVec 349 } 350 351 val lsqEnqCtrl = Module(new LsqEnqCtrl) 352 353 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 354 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 355 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 356 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 357 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 358 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 359 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 360} 361