1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles 9import xiangshan.backend.datapath.DataConfig.VAddrData 10import xiangshan.backend.regfile.RfWritePortWithConfig 11import xiangshan.backend.rename.BusyTable 12import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 13import xiangshan.backend.Bundles.{DynInst, IssueQueueWakeUpBundle} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numIntWb 24 val numVfStateWrite = backendParams.numVfWb 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 // params alias 39 private val LoadQueueSize = VirtualLoadQueueSize 40 41 val fromTop = new Bundle { 42 val hartId = Input(UInt(8.W)) 43 } 44 val fromWbFuBusyTable = new Bundle{ 45 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 46 } 47 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 48 49 val fromCtrlBlock = new Bundle { 50 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 51 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 52 val flush = Flipped(ValidIO(new Redirect)) 53 } 54 val fromDispatch = new Bundle { 55 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 56 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 57 } 58 val intWriteBack = MixedVec(Vec(backendParams.intPregParams.numWrite, 59 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 60 val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite, 61 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 62 val toDataPath: MixedVec[MixedVec[DecoupledIO[Bundles.IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 63 val fromDataPath: MixedVec[MixedVec[Bundles.OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 64 65 val fromSchedulers = new Bundle { 66 val wakeupVec: MixedVec[ValidIO[IssueQueueWakeUpBundle]] = Flipped(params.genWakeUpInValidBundle) 67 } 68 69 val toSchedulers = new Bundle { 70 val wakeupVec: MixedVec[ValidIO[IssueQueueWakeUpBundle]] = params.genWakeUpOutValidBundle 71 } 72 73 val memIO = if (params.isMemSchd) Some(new Bundle { 74 val lsqEnqIO = Flipped(new LsqEnqIO) 75 }) else None 76 val fromMem = if (params.isMemSchd) Some(new Bundle { 77 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 78 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 79 val stIssuePtr = Input(new SqPtr()) 80 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 81 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 82 // from lsq 83 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 84 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 85 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 86 }) else None 87 val toMem = if (params.isMemSchd) Some(new Bundle { 88 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 89 }) else None 90} 91 92abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 93 extends LazyModuleImp(wrapper) 94 with HasXSParameter 95{ 96 val io = IO(new SchedulerIO()) 97 98 // alias 99 private val iqWakeUpInMap: Map[String, ValidIO[IssueQueueWakeUpBundle]] = 100 io.fromSchedulers.wakeupVec.map(x => (x.bits.wakeupSource, x)).toMap 101 private val schdType = params.schdType 102 private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0)) 103 private val numPregs = params.numPregs 104 105 // Modules 106 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 107 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 108 109 // BusyTable Modules 110 val intBusyTable = schdType match { 111 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite))) 112 case _ => None 113 } 114 115 val vfBusyTable = schdType match { 116 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite))) 117 case _ => None 118 } 119 120 dispatch2Iq.io match { case dp2iq => 121 dp2iq.redirect <> io.fromCtrlBlock.flush 122 dp2iq.in <> io.fromDispatch.uops 123 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 124 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 125 } 126 127 intBusyTable match { 128 case Some(bt) => 129 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 130 btAllocPregs.valid := dpAllocPregs.isInt 131 btAllocPregs.bits := dpAllocPregs.preg 132 } 133 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 134 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 135 wb.bits := io.intWriteBack(i).addr 136 } 137 case None => 138 } 139 140 vfBusyTable match { 141 case Some(bt) => 142 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 143 btAllocPregs.valid := dpAllocPregs.isFp 144 btAllocPregs.bits := dpAllocPregs.preg 145 } 146 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 147 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 148 wb.bits := io.vfWriteBack(i).addr 149 } 150 case None => 151 } 152 153 val wakeupFromWBVec = Wire(Vec(params.numWakeupFromWB, ValidIO(new IssueQueueWakeUpBundle(params.pregIdxWidth)))) 154 val writeback = params.schdType match { 155 case IntScheduler() => io.intWriteBack 156 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 157 case VfScheduler() => io.vfWriteBack 158 case _ => Seq() 159 } 160 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 161 sink.valid := source.wen 162 sink.bits.rfWen := source.intWen 163 sink.bits.fpWen := source.fpWen 164 sink.bits.vecWen := source.vecWen 165 sink.bits.pdest := source.addr 166 } 167 168 // Connect bundles having the same wakeup source 169 issueQueues.foreach { iq => 170 iq.io.wakeupFromIQ.foreach { wakeUp => 171 wakeUp := iqWakeUpInMap(wakeUp.bits.wakeupSource) 172 } 173 } 174 175 private val iqWakeUpOutMap: Map[String, ValidIO[IssueQueueWakeUpBundle]] = 176 issueQueues.flatMap(_.io.wakeupToIQ) 177 .map(x => (x.bits.wakeupSource, x)) 178 .toMap 179 180 // Connect bundles having the same wakeup source 181 io.toSchedulers.wakeupVec.foreach { wakeUp => 182 wakeUp := iqWakeUpOutMap(wakeUp.bits.wakeupSource) 183 } 184 185 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 186 toDp <> issueQueues(i).io.deq 187 } 188 189 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(_.bits.wakeupSource)}") 190 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 191 192 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 193 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(_.bits.wakeupSource)}") 194} 195 196class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 197 extends SchedulerImpBase(wrapper) 198 with HasXSParameter 199{ 200// dontTouch(io.vfWbFuBusyTable) 201 println(s"[SchedulerArithImp] " + 202 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 203 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 204 205 issueQueues.zipWithIndex.foreach { case (iq, i) => 206 iq.io.flush <> io.fromCtrlBlock.flush 207 iq.io.enq <> dispatch2Iq.io.out(i) 208 iq.io.wakeupFromWB := wakeupFromWBVec 209 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 210 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 211 deqResp.bits.respType := RSFeedbackType.issueSuccess 212 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 213 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 214 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 215 216 } 217 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 218 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 219 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 220 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 221 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 222 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 223 224 } 225 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 226 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 227 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 228 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 229 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 230 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 231 232 } 233 234 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 235 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 236 } 237 238 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 239 case imp: IssueQueueIntImp => imp.io.enqJmp 240 case _ => None 241 }.filter(_.nonEmpty).flatMap(_.get) 242 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 243 244 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 245 iqJmp.pc := pc 246 iqJmp.target := target 247 } 248} 249 250class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 251 extends SchedulerImpBase(wrapper) 252 with HasXSParameter 253{ 254 println(s"[SchedulerMemImp] " + 255 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 256 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 257 258 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 259 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 260 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 261 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 262 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 263 264 issueQueues.zipWithIndex.foreach { case (iq, i) => 265 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 266 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 267 deqResp.bits.respType := RSFeedbackType.issueSuccess 268 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 269 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 270 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 271 272 } 273 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 274 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 275 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 276 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 277 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 278 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 279 280 } 281 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 282 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 283 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 284 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 285 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 286 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 287 288 } 289 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 290 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 291 } 292 293 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 294 iq.io.flush <> io.fromCtrlBlock.flush 295 iq.io.enq <> dispatch2Iq.io.out(i) 296 iq.io.wakeupFromWB := wakeupFromWBVec 297 } 298 299 ldAddrIQs.foreach { 300 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 301 case _ => 302 } 303 304 stAddrIQs.foreach { 305 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 306 case _ => 307 } 308 309 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 310 311 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 312 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 313 val isAllReady = staIQ.ready && stdIQ.ready 314 di.ready := isAllReady 315 staIQ.valid := di.valid && isAllReady 316 stdIQ.valid := di.valid && isAllReady 317 } 318 } 319 320 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 321 s"should be equal to number of data IQs(${stDataIQs})") 322 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 323 stdIQ.io.flush <> io.fromCtrlBlock.flush 324 325 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 326 stdIQEnq.bits := staIQEnq.bits 327 // Store data reuses store addr src(1) in dispatch2iq 328 // [dispatch2iq] --src*------src*(0)--> [staIQ] 329 // \ 330 // ---src*(1)--> [stdIQ] 331 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 332 // instead of dispatch2Iq.io.out(x).bits.src*(1) 333 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 334 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 335 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 336 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 337 } 338 stdIQ.io.wakeupFromWB := wakeupFromWBVec 339 } 340 341 val lsqEnqCtrl = Module(new LsqEnqCtrl) 342 343 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 344 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 345 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 346 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 347 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 348 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 349 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 350} 351