1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.regfile.RfWritePortWithConfig 13import xiangshan.backend.rename.BusyTable 14import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 15 16sealed trait SchedulerType 17 18case class IntScheduler() extends SchedulerType 19case class MemScheduler() extends SchedulerType 20case class VfScheduler() extends SchedulerType 21case class NoScheduler() extends SchedulerType 22 23class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 24 override def shouldBeInlined: Boolean = false 25 26 val numIntStateWrite = backendParams.numPregWb(IntData()) 27 val numVfStateWrite = backendParams.numPregWb(VecData()) 28 29 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 30 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 31 32 lazy val module: SchedulerImpBase = params.schdType match { 33 case IntScheduler() => new SchedulerArithImp(this)(params, p) 34 case MemScheduler() => new SchedulerMemImp(this)(params, p) 35 case VfScheduler() => new SchedulerArithImp(this)(params, p) 36 case _ => null 37 } 38} 39 40class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 41 // params alias 42 private val LoadQueueSize = VirtualLoadQueueSize 43 44 val fromTop = new Bundle { 45 val hartId = Input(UInt(8.W)) 46 } 47 val fromWbFuBusyTable = new Bundle{ 48 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 49 } 50 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 51 52 val fromCtrlBlock = new Bundle { 53 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 54 val flush = Flipped(ValidIO(new Redirect)) 55 } 56 val fromDispatch = new Bundle { 57 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 58 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 59 } 60 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 61 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 62 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 63 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 64 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 65 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 66 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 67 68 val fromSchedulers = new Bundle { 69 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 70 } 71 72 val toSchedulers = new Bundle { 73 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 74 } 75 76 val fromDataPath = new Bundle { 77 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 78 val og0Cancel = Input(ExuOH(backendParams.numExu)) 79 // Todo: remove this after no cancel signal from og1 80 val og1Cancel = Input(ExuOH(backendParams.numExu)) 81 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 82 // just be compatible to old code 83 def apply(i: Int)(j: Int) = resp(i)(j) 84 } 85 86 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 87 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 88 89 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 90 91 val memIO = if (params.isMemSchd) Some(new Bundle { 92 val lsqEnqIO = Flipped(new LsqEnqIO) 93 }) else None 94 val fromMem = if (params.isMemSchd) Some(new Bundle { 95 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 96 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 97 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 98 val stIssuePtr = Input(new SqPtr()) 99 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 100 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 101 val lqDeqPtr = Input(new LqPtr) 102 val sqDeqPtr = Input(new SqPtr) 103 // from lsq 104 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 105 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 106 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 107 }) else None 108 val toMem = if (params.isMemSchd) Some(new Bundle { 109 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 110 }) else None 111} 112 113abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 114 extends LazyModuleImp(wrapper) 115 with HasXSParameter 116{ 117 val io = IO(new SchedulerIO()) 118 119 // alias 120 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 121 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 122 private val schdType = params.schdType 123 124 // Modules 125 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 126 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 127 128 // BusyTable Modules 129 val intBusyTable = schdType match { 130 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 131 case _ => None 132 } 133 134 val vfBusyTable = schdType match { 135 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 136 case _ => None 137 } 138 139 dispatch2Iq.io match { case dp2iq => 140 dp2iq.redirect <> io.fromCtrlBlock.flush 141 dp2iq.in <> io.fromDispatch.uops 142 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 143 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 144 } 145 146 intBusyTable match { 147 case Some(bt) => 148 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 149 btAllocPregs.valid := dpAllocPregs.isInt 150 btAllocPregs.bits := dpAllocPregs.preg 151 } 152 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 153 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 154 wb.bits := io.intWriteBack(i).addr 155 } 156 bt.io.wakeUp := io.fromSchedulers.wakeupVec 157 bt.io.cancel := io.fromDataPath.cancelToBusyTable 158 case None => 159 } 160 161 vfBusyTable match { 162 case Some(bt) => 163 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 164 btAllocPregs.valid := dpAllocPregs.isFp 165 btAllocPregs.bits := dpAllocPregs.preg 166 } 167 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 168 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 169 wb.bits := io.vfWriteBack(i).addr 170 } 171 bt.io.wakeUp := io.fromSchedulers.wakeupVec 172 bt.io.cancel := io.fromDataPath.cancelToBusyTable 173 case None => 174 } 175 176 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 177 val writeback = params.schdType match { 178 case IntScheduler() => io.intWriteBack 179 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 180 case VfScheduler() => io.vfWriteBack 181 case _ => Seq() 182 } 183 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 184 sink.valid := source.wen 185 sink.bits.rfWen := source.intWen 186 sink.bits.fpWen := source.fpWen 187 sink.bits.vecWen := source.vecWen 188 sink.bits.pdest := source.addr 189 } 190 191 // Connect bundles having the same wakeup source 192 issueQueues.zipWithIndex.foreach { case(iq, i) => 193 iq.io.wakeupFromIQ.foreach { wakeUp => 194 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 195 } 196 iq.io.og0Cancel := io.fromDataPath.og0Cancel 197 iq.io.og1Cancel := io.fromDataPath.og1Cancel 198 iq.io.ldCancel := io.ldCancel 199 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 200 } 201 202 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 203 issueQueues.flatMap(_.io.wakeupToIQ) 204 .map(x => (x.bits.exuIdx, x)) 205 .toMap 206 207 // Connect bundles having the same wakeup source 208 io.toSchedulers.wakeupVec.foreach { wakeUp => 209 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 210 } 211 212 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 213 toDp <> issueQueues(i).io.deq 214 } 215 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 216 toDpDy <> issueQueues(i).io.deqDelay 217 } 218 219 // Response 220 issueQueues.zipWithIndex.foreach { case (iq, i) => 221 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 222 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 223 deqResp.bits.respType := RSFeedbackType.issueSuccess 224 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 225 deqResp.bits.uopIdx := iq.io.deq(j).bits.common.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)).vuopIdx 226 deqResp.bits.dataInvalidSqIdx := DontCare 227 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 228 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 229 } 230 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 231 og0Resp := io.fromDataPath(i)(j).og0resp 232 } 233 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 234 og1Resp := io.fromDataPath(i)(j).og1resp 235 } 236 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 237 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 238 finalIssueResp := io.loadFinalIssueResp(i)(j) 239 } else { 240 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 241 } 242 }) 243 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 244 memAddrIssueResp := io.memAddrIssueResp(i)(j) 245 }) 246 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 247 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 248 } 249 250 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 251 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 252 253 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 254 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 255} 256 257class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 258 extends SchedulerImpBase(wrapper) 259 with HasXSParameter 260{ 261// dontTouch(io.vfWbFuBusyTable) 262 println(s"[SchedulerArithImp] " + 263 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 264 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 265 266 issueQueues.zipWithIndex.foreach { case (iq, i) => 267 iq.io.flush <> io.fromCtrlBlock.flush 268 iq.io.enq <> dispatch2Iq.io.out(i) 269 iq.io.wakeupFromWB := wakeupFromWBVec 270 } 271} 272 273// FIXME: Vector mem instructions may not be handled properly! 274class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 275 extends SchedulerImpBase(wrapper) 276 with HasXSParameter 277{ 278 println(s"[SchedulerMemImp] " + 279 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 280 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 281 282 val memAddrIQs = issueQueues.filter(iq => iq.params.isMemAddrIQ) 283 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0 || iq.params.VstaCnt > 0) // included in memAddrIQs 284 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0 || iq.params.VlduCnt > 0) 285 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0 || iq.params.VstdCnt > 0) 286 val vecMemIQs = issueQueues.filter(iq => iq.params.isVecMemIQ) 287 val hyuIQs = issueQueues.filter(iq => iq.params.HyuCnt > 0) 288 289 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 290 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 291 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 292 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 293 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 294 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 295 296 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 297 298 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 299 iq.io.flush <> io.fromCtrlBlock.flush 300 iq.io.enq <> dispatch2Iq.io.out(i) 301 iq.io.wakeupFromWB := wakeupFromWBVec 302 } 303 304 ldAddrIQs.zipWithIndex.foreach { 305 case (imp: IssueQueueMemAddrImp, i) => 306 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 307 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 308 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 309 case _ => 310 } 311 312 stAddrIQs.zipWithIndex.foreach { 313 case (imp: IssueQueueMemAddrImp, i) => 314 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 315 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 316 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 317 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 318 case _ => 319 } 320 321 hyuIQs.foreach { 322 case imp: IssueQueueMemAddrImp => 323 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 324 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 325 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 326 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 327 case _ => 328 } 329 330 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 331 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 332 333 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 334 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 335 336 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 337 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 338 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 339 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 340 341 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 342 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 343 344 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 345 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 346 347 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 348 dispatch2Iq.io.out(idxInSchBlk).zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 349 val isAllReady = staIQ.ready && stdIQ.ready 350 dp.ready := isAllReady 351 staIQ.valid := dp.valid && isAllReady 352 stdIQ.valid := dp.valid && isAllReady && FuType.isStore(dp.bits.fuType) 353 } 354 } 355 356 for ((idxInSchBlk, i) <- hyaIdxSeq.zipWithIndex) { 357 dispatch2Iq.io.out(idxInSchBlk).zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 358 val isAllReady = hyaIQ.ready && hydIQ.ready 359 dp.ready := isAllReady 360 hyaIQ.valid := dp.valid && isAllReady 361 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 362 } 363 } 364 365 stDataIQs.zipWithIndex.foreach { case (iq, i) => 366 iq.io.flush <> io.fromCtrlBlock.flush 367 iq.io.wakeupFromWB := wakeupFromWBVec 368 } 369 370 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 371 stdIQEnq.bits := staIQEnq.bits 372 // Store data reuses store addr src(1) in dispatch2iq 373 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 374 // \ 375 // ---src*(1)--> [stdIQ] 376 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 377 // instead of dispatch2Iq.io.out(x).bits.src*(1) 378 val stdIdx = 1 379 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 380 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 381 stdIQEnq.bits.dataSource(0) := staIQEnq.bits.dataSource(stdIdx) 382 stdIQEnq.bits.l1ExuOH(0) := staIQEnq.bits.l1ExuOH(stdIdx) 383 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 384 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 385 } 386 387 vecMemIQs.foreach { 388 case imp: IssueQueueVecMemImp => 389 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 390 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 391 // not used 392 imp.io.memIO.get.feedbackIO := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO) 393 // maybe not used 394 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 395 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 396 case _ => 397 } 398 399 val lsqEnqCtrl = Module(new LsqEnqCtrl) 400 401 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 402 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 403 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 404 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 405 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 406 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 407 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 408} 409