1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.regfile.RfWritePortWithConfig 14import xiangshan.backend.rename.BusyTable 15import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 16 17sealed trait SchedulerType 18 19case class IntScheduler() extends SchedulerType 20case class MemScheduler() extends SchedulerType 21case class VfScheduler() extends SchedulerType 22case class NoScheduler() extends SchedulerType 23 24class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 25 override def shouldBeInlined: Boolean = false 26 27 val numIntStateWrite = backendParams.numPregWb(IntData()) 28 val numVfStateWrite = backendParams.numPregWb(VecData()) 29 30 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 31 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 32 33 lazy val module: SchedulerImpBase = params.schdType match { 34 case IntScheduler() => new SchedulerArithImp(this)(params, p) 35 case MemScheduler() => new SchedulerMemImp(this)(params, p) 36 case VfScheduler() => new SchedulerArithImp(this)(params, p) 37 case _ => null 38 } 39} 40 41class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 42 // params alias 43 private val LoadQueueSize = VirtualLoadQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 val IQValidNumVec = Output(MixedVec(backendParams.genIQValidNumBundle)) 53 54 val fromCtrlBlock = new Bundle { 55 val flush = Flipped(ValidIO(new Redirect)) 56 } 57 val fromDispatch = new Bundle { 58 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 59 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 60 } 61 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 62 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 63 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 64 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 65 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 66 67 val fromSchedulers = new Bundle { 68 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 69 } 70 71 val toSchedulers = new Bundle { 72 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 73 } 74 75 val fromDataPath = new Bundle { 76 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 77 val og0Cancel = Input(ExuOH(backendParams.numExu)) 78 // Todo: remove this after no cancel signal from og1 79 val og1Cancel = Input(ExuOH(backendParams.numExu)) 80 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 81 // just be compatible to old code 82 def apply(i: Int)(j: Int) = resp(i)(j) 83 } 84 85 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 86 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 87 88 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 89 90 val memIO = if (params.isMemSchd) Some(new Bundle { 91 val lsqEnqIO = Flipped(new LsqEnqIO) 92 }) else None 93 val fromMem = if (params.isMemSchd) Some(new Bundle { 94 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 95 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 96 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 97 val stIssuePtr = Input(new SqPtr()) 98 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 99 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 100 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 101 val lqDeqPtr = Input(new LqPtr) 102 val sqDeqPtr = Input(new SqPtr) 103 // from lsq 104 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 105 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 106 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 107 }) else None 108 val toMem = if (params.isMemSchd) Some(new Bundle { 109 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 110 }) else None 111} 112 113abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 114 extends LazyModuleImp(wrapper) 115 with HasXSParameter 116{ 117 val io = IO(new SchedulerIO()) 118 119 // alias 120 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 121 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 122 private val schdType = params.schdType 123 124 // Modules 125 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 126 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 127 if (params.isIntSchd) { 128 dispatch2Iq.io.IQValidNumVec.get := io.IQValidNumVec 129 io.IQValidNumVec := MixedVecInit(issueQueues.map(_.io.validCntDeqVec)) 130 } 131 else io.IQValidNumVec := 0.U.asTypeOf(io.IQValidNumVec) 132 133 // valid count 134 dispatch2Iq.io.iqValidCnt := issueQueues.filter(_.params.StdCnt == 0).map(_.io.status.validCnt) 135 136 // BusyTable Modules 137 val intBusyTable = schdType match { 138 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 139 case _ => None 140 } 141 142 val vfBusyTable = schdType match { 143 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 144 case _ => None 145 } 146 147 dispatch2Iq.io match { case dp2iq => 148 dp2iq.redirect <> io.fromCtrlBlock.flush 149 dp2iq.in <> io.fromDispatch.uops 150 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 151 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 152 } 153 154 intBusyTable match { 155 case Some(bt) => 156 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 157 btAllocPregs.valid := dpAllocPregs.isInt 158 btAllocPregs.bits := dpAllocPregs.preg 159 } 160 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 161 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 162 wb.bits := io.intWriteBack(i).addr 163 } 164 bt.io.wakeUp := io.fromSchedulers.wakeupVec 165 bt.io.cancel := io.fromDataPath.cancelToBusyTable 166 bt.io.ldCancel := io.ldCancel 167 case None => 168 } 169 170 vfBusyTable match { 171 case Some(bt) => 172 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 173 btAllocPregs.valid := dpAllocPregs.isFp 174 btAllocPregs.bits := dpAllocPregs.preg 175 } 176 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 177 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 178 wb.bits := io.vfWriteBack(i).addr 179 } 180 bt.io.wakeUp := io.fromSchedulers.wakeupVec 181 bt.io.cancel := io.fromDataPath.cancelToBusyTable 182 bt.io.ldCancel := io.ldCancel 183 case None => 184 } 185 186 val wakeupFromIntWBVec = Wire(params.genIntWBWakeUpSinkValidBundle) 187 val wakeupFromVfWBVec = Wire(params.genVfWBWakeUpSinkValidBundle) 188 189 wakeupFromIntWBVec.zip(io.intWriteBack).foreach { case (sink, source) => 190 sink.valid := source.wen 191 sink.bits.rfWen := source.intWen 192 sink.bits.fpWen := source.fpWen 193 sink.bits.vecWen := source.vecWen 194 sink.bits.pdest := source.addr 195 } 196 197 wakeupFromVfWBVec.zip(io.vfWriteBack).foreach { case (sink, source) => 198 sink.valid := source.wen 199 sink.bits.rfWen := source.intWen 200 sink.bits.fpWen := source.fpWen 201 sink.bits.vecWen := source.vecWen 202 sink.bits.pdest := source.addr 203 } 204 205 // Connect bundles having the same wakeup source 206 issueQueues.zipWithIndex.foreach { case(iq, i) => 207 iq.io.wakeupFromIQ.foreach { wakeUp => 208 val wakeUpIn = iqWakeUpInMap(wakeUp.bits.exuIdx) 209 val exuIdx = wakeUp.bits.exuIdx 210 println(s"[Backend] Connect wakeup exuIdx ${exuIdx}") 211 connectSamePort(wakeUp,wakeUpIn) 212 backendParams.connectWakeup(exuIdx) 213 if (backendParams.isCopyPdest(exuIdx)) { 214 println(s"[Backend] exuIdx ${exuIdx} use pdestCopy ${backendParams.getCopyPdestIndex(exuIdx)}") 215 wakeUp.bits.pdest := wakeUpIn.bits.pdestCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 216 if (wakeUpIn.bits.rfWenCopy.nonEmpty) wakeUp.bits.rfWen := wakeUpIn.bits.rfWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 217 if (wakeUpIn.bits.fpWenCopy.nonEmpty) wakeUp.bits.fpWen := wakeUpIn.bits.fpWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 218 if (wakeUpIn.bits.vecWenCopy.nonEmpty) wakeUp.bits.vecWen := wakeUpIn.bits.vecWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 219 if (wakeUpIn.bits.loadDependencyCopy.nonEmpty) wakeUp.bits.loadDependency := wakeUpIn.bits.loadDependencyCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 220 } 221 if (iq.params.numIntSrc == 0) wakeUp.bits.rfWen := false.B 222 if (iq.params.numFpSrc == 0) wakeUp.bits.fpWen := false.B 223 if (iq.params.numVfSrc == 0) wakeUp.bits.vecWen := false.B 224 } 225 iq.io.og0Cancel := io.fromDataPath.og0Cancel 226 iq.io.og1Cancel := io.fromDataPath.og1Cancel 227 iq.io.ldCancel := io.ldCancel 228 } 229 230 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 231 issueQueues.flatMap(_.io.wakeupToIQ) 232 .map(x => (x.bits.exuIdx, x)) 233 .toMap 234 235 // Connect bundles having the same wakeup source 236 io.toSchedulers.wakeupVec.foreach { wakeUp => 237 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 238 } 239 240 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 241 toDpDy <> issueQueues(i).io.deqDelay 242 } 243 244 // Response 245 issueQueues.zipWithIndex.foreach { case (iq, i) => 246 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 247 og0Resp := io.fromDataPath(i)(j).og0resp 248 } 249 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 250 og1Resp := io.fromDataPath(i)(j).og1resp 251 } 252 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 253 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 254 finalIssueResp := io.loadFinalIssueResp(i)(j) 255 } else { 256 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 257 } 258 }) 259 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 260 if (io.memAddrIssueResp(i).isDefinedAt(j)) { 261 memAddrIssueResp := io.memAddrIssueResp(i)(j) 262 } else { 263 memAddrIssueResp := 0.U.asTypeOf(memAddrIssueResp) 264 } 265 }) 266 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 267 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 268 } 269 270 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 271 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 272 273 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 274 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 275} 276 277class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 278 extends SchedulerImpBase(wrapper) 279 with HasXSParameter 280{ 281// dontTouch(io.vfWbFuBusyTable) 282 println(s"[SchedulerArithImp] " + 283 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 284 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 285 286 issueQueues.zipWithIndex.foreach { case (iq, i) => 287 iq.io.flush <> io.fromCtrlBlock.flush 288 iq.io.enq <> dispatch2Iq.io.out(i) 289 val intWBIQ = params.schdType match { 290 case IntScheduler() => wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) 291 case VfScheduler() => wakeupFromVfWBVec 292 case _ => null 293 } 294 iq.io.wakeupFromWB.zip(intWBIQ).foreach{ case (sink, source) => sink := source} 295 } 296} 297 298// FIXME: Vector mem instructions may not be handled properly! 299class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 300 extends SchedulerImpBase(wrapper) 301 with HasXSParameter 302{ 303 println(s"[SchedulerMemImp] " + 304 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 305 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 306 307 val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ) 308 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 309 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 310 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 311 val vecMemIQs = issueQueues.filter(_.params.isVecMemIQ) 312 val (hyuIQs, hyuIQIdxs) = issueQueues.zipWithIndex.filter(_._1.params.HyuCnt > 0).unzip 313 314 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 315 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 316 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 317 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 318 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 319 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 320 321 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 322 323 private val loadWakeUp = issueQueues.filter(_.params.LdExuCnt > 0).map(_.asInstanceOf[IssueQueueMemAddrImp].io.memIO.get.loadWakeUp).flatten 324 require(loadWakeUp.length == io.fromMem.get.wakeup.length) 325 loadWakeUp.zip(io.fromMem.get.wakeup).foreach(x => x._1 := x._2) 326 327 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 328 iq.io.flush <> io.fromCtrlBlock.flush 329 iq.io.enq <> dispatch2Iq.io.out(i) 330 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 331 } 332 333 ldAddrIQs.zipWithIndex.foreach { 334 case (imp: IssueQueueMemAddrImp, i) => 335 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 336 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 337 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 338 case _ => 339 } 340 341 stAddrIQs.zipWithIndex.foreach { 342 case (imp: IssueQueueMemAddrImp, i) => 343 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 344 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 345 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 346 case _ => 347 } 348 349 hyuIQs.zip(hyuIQIdxs).foreach { 350 case (imp: IssueQueueMemAddrImp, idx) => 351 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 352 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 353 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 354 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 355 // TODO: refactor ditry code 356 imp.io.deqDelay(1).ready := false.B 357 io.toDataPathAfterDelay(idx)(1).valid := false.B 358 io.toDataPathAfterDelay(idx)(1).bits := 0.U.asTypeOf(io.toDataPathAfterDelay(idx)(1).bits) 359 case _ => 360 } 361 362 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 363 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 364 365 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 366 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 367 368 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 369 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 370 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 371 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 372 373 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 374 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 375 376 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 377 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 378 379 val d2IqStaOut = dispatch2Iq.io.out.zipWithIndex.filter(staIdxSeq contains _._2).unzip._1.flatten 380 d2IqStaOut.zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 381 val isAllReady = staIQ.ready && stdIQ.ready 382 dp.ready := isAllReady 383 staIQ.valid := dp.valid && isAllReady 384 stdIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 385 } 386 387 val d2IqHyaOut = dispatch2Iq.io.out.zipWithIndex.filter(hyaIdxSeq contains _._2).unzip._1.flatten 388 d2IqHyaOut.zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 389 val isAllReady = hyaIQ.ready && hydIQ.ready 390 dp.ready := isAllReady 391 hyaIQ.valid := dp.valid && isAllReady 392 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 393 } 394 395 stDataIQs.zipWithIndex.foreach { case (iq, i) => 396 iq.io.flush <> io.fromCtrlBlock.flush 397 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 398 } 399 400 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 401 stdIQEnq.bits := staIQEnq.bits 402 // Store data reuses store addr src(1) in dispatch2iq 403 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 404 // \ 405 // ---src*(1)--> [stdIQ] 406 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 407 // instead of dispatch2Iq.io.out(x).bits.src*(1) 408 val stdIdx = 1 409 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 410 stdIQEnq.bits.srcLoadDependency(0) := staIQEnq.bits.srcLoadDependency(1) 411 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 412 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 413 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 414 } 415 416 vecMemIQs.foreach { 417 case imp: IssueQueueVecMemImp => 418 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 419 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 420 // not used 421 imp.io.memIO.get.feedbackIO := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO) 422 // maybe not used 423 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 424 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 425 imp.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => imp.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 426 427 case _ => 428 } 429 430 val lsqEnqCtrl = Module(new LsqEnqCtrl) 431 432 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 433 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 434 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 435 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 436 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 437 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 438 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 439} 440