1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.regfile.RfWritePortWithConfig 12import xiangshan.backend.rename.BusyTable 13import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numPregWb(IntData()) 24 val numVfStateWrite = backendParams.numPregWb(VecData()) 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 // params alias 39 private val LoadQueueSize = VirtualLoadQueueSize 40 41 val fromTop = new Bundle { 42 val hartId = Input(UInt(8.W)) 43 } 44 val fromWbFuBusyTable = new Bundle{ 45 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 46 } 47 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 48 49 val fromCtrlBlock = new Bundle { 50 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 51 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 52 val flush = Flipped(ValidIO(new Redirect)) 53 } 54 val fromDispatch = new Bundle { 55 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 56 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 57 } 58 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 59 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 60 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 61 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 62 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 63 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 64 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 65 66 val fromSchedulers = new Bundle { 67 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 68 } 69 70 val toSchedulers = new Bundle { 71 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 72 } 73 74 val fromDataPath = new Bundle { 75 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 76 val og0Cancel = Input(ExuVec(backendParams.numExu)) 77 // Todo: remove this after no cancel signal from og1 78 val og1Cancel = Input(ExuVec(backendParams.numExu)) 79 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 80 // just be compatible to old code 81 def apply(i: Int)(j: Int) = resp(i)(j) 82 } 83 84 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 85 86 val ldCancel = Vec(backendParams.LduCnt, Flipped(new LoadCancelIO)) 87 88 val memIO = if (params.isMemSchd) Some(new Bundle { 89 val lsqEnqIO = Flipped(new LsqEnqIO) 90 }) else None 91 val fromMem = if (params.isMemSchd) Some(new Bundle { 92 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 93 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 94 val stIssuePtr = Input(new SqPtr()) 95 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 96 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 97 // from lsq 98 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 99 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 100 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 101 }) else None 102 val toMem = if (params.isMemSchd) Some(new Bundle { 103 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 104 }) else None 105} 106 107abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 108 extends LazyModuleImp(wrapper) 109 with HasXSParameter 110{ 111 val io = IO(new SchedulerIO()) 112 113 // alias 114 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 115 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 116 private val schdType = params.schdType 117 118 // Modules 119 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 120 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 121 122 // BusyTable Modules 123 val intBusyTable = schdType match { 124 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 125 case _ => None 126 } 127 128 val vfBusyTable = schdType match { 129 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 130 case _ => None 131 } 132 133 dispatch2Iq.io match { case dp2iq => 134 dp2iq.redirect <> io.fromCtrlBlock.flush 135 dp2iq.in <> io.fromDispatch.uops 136 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 137 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 138 } 139 140 intBusyTable match { 141 case Some(bt) => 142 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 143 btAllocPregs.valid := dpAllocPregs.isInt 144 btAllocPregs.bits := dpAllocPregs.preg 145 } 146 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 147 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 148 wb.bits := io.intWriteBack(i).addr 149 } 150 bt.io.wakeUp := io.fromSchedulers.wakeupVec 151 bt.io.cancel := io.fromDataPath.cancelToBusyTable 152 case None => 153 } 154 155 vfBusyTable match { 156 case Some(bt) => 157 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 158 btAllocPregs.valid := dpAllocPregs.isFp 159 btAllocPregs.bits := dpAllocPregs.preg 160 } 161 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 162 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 163 wb.bits := io.vfWriteBack(i).addr 164 } 165 bt.io.wakeUp := io.fromSchedulers.wakeupVec 166 bt.io.cancel := io.fromDataPath.cancelToBusyTable 167 case None => 168 } 169 170 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 171 val writeback = params.schdType match { 172 case IntScheduler() => io.intWriteBack 173 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 174 case VfScheduler() => io.vfWriteBack 175 case _ => Seq() 176 } 177 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 178 sink.valid := source.wen 179 sink.bits.rfWen := source.intWen 180 sink.bits.fpWen := source.fpWen 181 sink.bits.vecWen := source.vecWen 182 sink.bits.pdest := source.addr 183 } 184 185 // Connect bundles having the same wakeup source 186 issueQueues.zipWithIndex.foreach { case(iq, i) => 187 iq.io.wakeupFromIQ.foreach { wakeUp => 188 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 189 } 190 iq.io.og0Cancel := io.fromDataPath.og0Cancel 191 iq.io.og1Cancel := io.fromDataPath.og1Cancel 192 iq.io.ldCancel := io.ldCancel 193 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 194 } 195 196 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 197 issueQueues.flatMap(_.io.wakeupToIQ) 198 .map(x => (x.bits.exuIdx, x)) 199 .toMap 200 201 // Connect bundles having the same wakeup source 202 io.toSchedulers.wakeupVec.foreach { wakeUp => 203 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 204 } 205 206 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 207 toDp <> issueQueues(i).io.deq 208 } 209 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 210 toDpDy <> issueQueues(i).io.deqDelay 211 } 212 213 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 214 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 215 216 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 217 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 218} 219 220class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 221 extends SchedulerImpBase(wrapper) 222 with HasXSParameter 223{ 224// dontTouch(io.vfWbFuBusyTable) 225 println(s"[SchedulerArithImp] " + 226 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 227 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 228 229 issueQueues.zipWithIndex.foreach { case (iq, i) => 230 iq.io.flush <> io.fromCtrlBlock.flush 231 iq.io.enq <> dispatch2Iq.io.out(i) 232 iq.io.wakeupFromWB := wakeupFromWBVec 233 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 234 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 235 deqResp.bits.respType := RSFeedbackType.issueSuccess 236 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 237 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 238 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 239 240 } 241 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 242 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 243 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 244 og0Resp.bits.robIdx := io.fromDataPath(i)(j).og0resp.bits.robIdx 245 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 246 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 247 248 } 249 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 250 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 251 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 252 og1Resp.bits.robIdx := io.fromDataPath(i)(j).og1resp.bits.robIdx 253 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 254 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 255 256 } 257 258 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 259 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 260 } 261 262 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 263 case imp: IssueQueueIntImp => imp.io.enqJmp 264 case _ => None 265 }.filter(_.nonEmpty).flatMap(_.get) 266 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 267 268 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 269 iqJmp.pc := pc 270 iqJmp.target := target 271 } 272} 273 274class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 275 extends SchedulerImpBase(wrapper) 276 with HasXSParameter 277{ 278 println(s"[SchedulerMemImp] " + 279 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 280 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 281 282 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 283 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 284 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 285 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 286 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 287 288 issueQueues.zipWithIndex.foreach { case (iq, i) => 289 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 290 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 291 deqResp.bits.respType := RSFeedbackType.issueSuccess 292 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 293 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 294 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 295 296 } 297 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 298 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 299 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 300 og0Resp.bits.robIdx := io.fromDataPath(i)(j).og0resp.bits.robIdx 301 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 302 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 303 304 } 305 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 306 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 307 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 308 og1Resp.bits.robIdx := io.fromDataPath(i)(j).og1resp.bits.robIdx 309 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 310 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 311 312 } 313 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 314 finalIssueResp := io.loadFinalIssueResp(i)(j) 315 }) 316 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 317 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 318 } 319 320 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 321 iq.io.flush <> io.fromCtrlBlock.flush 322 iq.io.enq <> dispatch2Iq.io.out(i) 323 iq.io.wakeupFromWB := wakeupFromWBVec 324 } 325 326 ldAddrIQs.foreach { 327 case imp: IssueQueueMemAddrImp => 328 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 329 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 330 case _ => 331 } 332 333 stAddrIQs.foreach { 334 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 335 case _ => 336 } 337 338 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 339 340 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 341 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 342 val isAllReady = staIQ.ready && stdIQ.ready 343 di.ready := isAllReady 344 staIQ.valid := di.valid && isAllReady 345 stdIQ.valid := di.valid && isAllReady 346 } 347 } 348 349 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 350 s"should be equal to number of data IQs(${stDataIQs})") 351 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 352 stdIQ.io.flush <> io.fromCtrlBlock.flush 353 354 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 355 stdIQEnq.bits := staIQEnq.bits 356 // Store data reuses store addr src(1) in dispatch2iq 357 // [dispatch2iq] --src*------src*(0)--> [staIQ] 358 // \ 359 // ---src*(1)--> [stdIQ] 360 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 361 // instead of dispatch2Iq.io.out(x).bits.src*(1) 362 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 363 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 364 stdIQEnq.bits.dataSource(0) := staIQEnq.bits.dataSource(1) 365 stdIQEnq.bits.l1ExuOH(0) := staIQEnq.bits.l1ExuOH(1) 366 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 367 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 368 } 369 stdIQ.io.wakeupFromWB := wakeupFromWBVec 370 } 371 372 val lsqEnqCtrl = Module(new LsqEnqCtrl) 373 374 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 375 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 376 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 377 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 378 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 379 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 380 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 381} 382