1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.regfile.RfWritePortWithConfig 12import xiangshan.backend.rename.BusyTable 13import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 override def shouldBeInlined: Boolean = false 24 25 val numIntStateWrite = backendParams.numPregWb(IntData()) 26 val numVfStateWrite = backendParams.numPregWb(VecData()) 27 28 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 29 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 30 31 lazy val module: SchedulerImpBase = params.schdType match { 32 case IntScheduler() => new SchedulerArithImp(this)(params, p) 33 case MemScheduler() => new SchedulerMemImp(this)(params, p) 34 case VfScheduler() => new SchedulerArithImp(this)(params, p) 35 case _ => null 36 } 37} 38 39class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 40 // params alias 41 private val LoadQueueSize = VirtualLoadQueueSize 42 43 val fromTop = new Bundle { 44 val hartId = Input(UInt(8.W)) 45 } 46 val fromWbFuBusyTable = new Bundle{ 47 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 48 } 49 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 50 51 val fromCtrlBlock = new Bundle { 52 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 53 val flush = Flipped(ValidIO(new Redirect)) 54 } 55 val fromDispatch = new Bundle { 56 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 57 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 58 } 59 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 60 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 61 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 62 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 63 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 64 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 65 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 66 67 val fromSchedulers = new Bundle { 68 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 69 } 70 71 val toSchedulers = new Bundle { 72 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 73 } 74 75 val fromDataPath = new Bundle { 76 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 77 val og0Cancel = Input(ExuVec(backendParams.numExu)) 78 // Todo: remove this after no cancel signal from og1 79 val og1Cancel = Input(ExuVec(backendParams.numExu)) 80 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 81 // just be compatible to old code 82 def apply(i: Int)(j: Int) = resp(i)(j) 83 } 84 85 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 86 87 val ldCancel = Vec(backendParams.LduCnt, Flipped(new LoadCancelIO)) 88 89 val memIO = if (params.isMemSchd) Some(new Bundle { 90 val lsqEnqIO = Flipped(new LsqEnqIO) 91 }) else None 92 val fromMem = if (params.isMemSchd) Some(new Bundle { 93 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 94 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 95 val stIssuePtr = Input(new SqPtr()) 96 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 97 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 98 // from lsq 99 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 100 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 101 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 102 }) else None 103 val toMem = if (params.isMemSchd) Some(new Bundle { 104 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 105 }) else None 106} 107 108abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 109 extends LazyModuleImp(wrapper) 110 with HasXSParameter 111{ 112 val io = IO(new SchedulerIO()) 113 114 // alias 115 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 116 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 117 private val schdType = params.schdType 118 119 // Modules 120 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 121 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 122 123 // BusyTable Modules 124 val intBusyTable = schdType match { 125 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 126 case _ => None 127 } 128 129 val vfBusyTable = schdType match { 130 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 131 case _ => None 132 } 133 134 dispatch2Iq.io match { case dp2iq => 135 dp2iq.redirect <> io.fromCtrlBlock.flush 136 dp2iq.in <> io.fromDispatch.uops 137 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 138 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 139 } 140 141 intBusyTable match { 142 case Some(bt) => 143 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 144 btAllocPregs.valid := dpAllocPregs.isInt 145 btAllocPregs.bits := dpAllocPregs.preg 146 } 147 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 148 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 149 wb.bits := io.intWriteBack(i).addr 150 } 151 bt.io.wakeUp := io.fromSchedulers.wakeupVec 152 bt.io.cancel := io.fromDataPath.cancelToBusyTable 153 case None => 154 } 155 156 vfBusyTable match { 157 case Some(bt) => 158 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 159 btAllocPregs.valid := dpAllocPregs.isFp 160 btAllocPregs.bits := dpAllocPregs.preg 161 } 162 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 163 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 164 wb.bits := io.vfWriteBack(i).addr 165 } 166 bt.io.wakeUp := io.fromSchedulers.wakeupVec 167 bt.io.cancel := io.fromDataPath.cancelToBusyTable 168 case None => 169 } 170 171 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 172 val writeback = params.schdType match { 173 case IntScheduler() => io.intWriteBack 174 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 175 case VfScheduler() => io.vfWriteBack 176 case _ => Seq() 177 } 178 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 179 sink.valid := source.wen 180 sink.bits.rfWen := source.intWen 181 sink.bits.fpWen := source.fpWen 182 sink.bits.vecWen := source.vecWen 183 sink.bits.pdest := source.addr 184 } 185 186 // Connect bundles having the same wakeup source 187 issueQueues.zipWithIndex.foreach { case(iq, i) => 188 iq.io.wakeupFromIQ.foreach { wakeUp => 189 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 190 } 191 iq.io.og0Cancel := io.fromDataPath.og0Cancel 192 iq.io.og1Cancel := io.fromDataPath.og1Cancel 193 iq.io.ldCancel := io.ldCancel 194 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 195 } 196 197 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 198 issueQueues.flatMap(_.io.wakeupToIQ) 199 .map(x => (x.bits.exuIdx, x)) 200 .toMap 201 202 // Connect bundles having the same wakeup source 203 io.toSchedulers.wakeupVec.foreach { wakeUp => 204 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 205 } 206 207 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 208 toDp <> issueQueues(i).io.deq 209 } 210 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 211 toDpDy <> issueQueues(i).io.deqDelay 212 } 213 214 // Response 215 issueQueues.zipWithIndex.foreach { case (iq, i) => 216 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 217 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 218 deqResp.bits.respType := RSFeedbackType.issueSuccess 219 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 220 deqResp.bits.dataInvalidSqIdx := DontCare 221 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 222 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 223 } 224 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 225 og0Resp := io.fromDataPath(i)(j).og0resp 226 } 227 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 228 og1Resp := io.fromDataPath(i)(j).og1resp 229 } 230 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 231 finalIssueResp := io.loadFinalIssueResp(i)(j) 232 }) 233 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 234 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 235 } 236 237 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 238 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 239 240 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 241 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 242} 243 244class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 245 extends SchedulerImpBase(wrapper) 246 with HasXSParameter 247{ 248// dontTouch(io.vfWbFuBusyTable) 249 println(s"[SchedulerArithImp] " + 250 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 251 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 252 253 issueQueues.zipWithIndex.foreach { case (iq, i) => 254 iq.io.flush <> io.fromCtrlBlock.flush 255 iq.io.enq <> dispatch2Iq.io.out(i) 256 iq.io.wakeupFromWB := wakeupFromWBVec 257 } 258} 259 260// FIXME: Vector mem instructions may not be handled properly! 261class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 262 extends SchedulerImpBase(wrapper) 263 with HasXSParameter 264{ 265 println(s"[SchedulerMemImp] " + 266 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 267 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 268 269 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 270 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 271 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 272 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 273 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 274 275 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 276 277 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 278 iq.io.flush <> io.fromCtrlBlock.flush 279 iq.io.enq <> dispatch2Iq.io.out(i) 280 iq.io.wakeupFromWB := wakeupFromWBVec 281 } 282 283 ldAddrIQs.foreach { 284 case imp: IssueQueueMemAddrImp => 285 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 286 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 287 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 288 case _ => 289 } 290 291 stAddrIQs.foreach { 292 case imp: IssueQueueMemAddrImp => 293 imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 294 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 295 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 296 case _ => 297 } 298 299 // TODO: Implement vstu 300 issueQueues.filter(iq => iq.params.VstuCnt > 0).foreach { 301 case imp: IssueQueueMemAddrImp => 302 imp.io.memIO.get.feedbackIO <> DontCare 303 imp.io.memIO.get.checkWait.stIssuePtr := DontCare 304 imp.io.memIO.get.checkWait.memWaitUpdateReq := DontCare 305 case _ => 306 } 307 308 // TODO: Implement vldu 309 issueQueues.filter(iq => iq.params.VlduCnt > 0).foreach { 310 case imp: IssueQueueMemAddrImp => 311 imp.io.memIO.get.feedbackIO <> DontCare 312 imp.io.memIO.get.checkWait.stIssuePtr := DontCare 313 imp.io.memIO.get.checkWait.memWaitUpdateReq := DontCare 314 case _ => 315 } 316 317 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 318 319 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 320 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 321 val isAllReady = staIQ.ready && stdIQ.ready 322 di.ready := isAllReady 323 staIQ.valid := di.valid && isAllReady 324 stdIQ.valid := di.valid && isAllReady 325 } 326 } 327 328 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 329 s"should be equal to number of data IQs(${stDataIQs})") 330 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 331 stdIQ.io.flush <> io.fromCtrlBlock.flush 332 333 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 334 stdIQEnq.bits := staIQEnq.bits 335 // Store data reuses store addr src(1) in dispatch2iq 336 // [dispatch2iq] --src*------src*(0)--> [staIQ] 337 // \ 338 // ---src*(1)--> [stdIQ] 339 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 340 // instead of dispatch2Iq.io.out(x).bits.src*(1) 341 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 342 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 343 stdIQEnq.bits.dataSource(0) := staIQEnq.bits.dataSource(1) 344 stdIQEnq.bits.l1ExuOH(0) := staIQEnq.bits.l1ExuOH(1) 345 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 346 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 347 } 348 stdIQ.io.wakeupFromWB := wakeupFromWBVec 349 } 350 351 val lsqEnqCtrl = Module(new LsqEnqCtrl) 352 353 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 354 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 355 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 356 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 357 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 358 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 359 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 360} 361