1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.regfile.RfWritePortWithConfig 14import xiangshan.backend.rename.BusyTable 15import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 16 17sealed trait SchedulerType 18 19case class IntScheduler() extends SchedulerType 20case class MemScheduler() extends SchedulerType 21case class VfScheduler() extends SchedulerType 22case class NoScheduler() extends SchedulerType 23 24class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 25 override def shouldBeInlined: Boolean = false 26 27 val numIntStateWrite = backendParams.numPregWb(IntData()) 28 val numVfStateWrite = backendParams.numPregWb(VecData()) 29 30 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 31 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 32 33 lazy val module: SchedulerImpBase = params.schdType match { 34 case IntScheduler() => new SchedulerArithImp(this)(params, p) 35 case MemScheduler() => new SchedulerMemImp(this)(params, p) 36 case VfScheduler() => new SchedulerArithImp(this)(params, p) 37 case _ => null 38 } 39} 40 41class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 42 // params alias 43 private val LoadQueueSize = VirtualLoadQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 val IQValidNumVec = Output(MixedVec(backendParams.genIQValidNumBundle)) 53 54 val fromCtrlBlock = new Bundle { 55 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 56 val flush = Flipped(ValidIO(new Redirect)) 57 } 58 val fromDispatch = new Bundle { 59 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 60 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 61 } 62 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 63 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 64 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 65 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 66 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 67 68 val fromSchedulers = new Bundle { 69 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 70 } 71 72 val toSchedulers = new Bundle { 73 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 74 } 75 76 val fromDataPath = new Bundle { 77 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 78 val og0Cancel = Input(ExuOH(backendParams.numExu)) 79 // Todo: remove this after no cancel signal from og1 80 val og1Cancel = Input(ExuOH(backendParams.numExu)) 81 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 82 // just be compatible to old code 83 def apply(i: Int)(j: Int) = resp(i)(j) 84 } 85 86 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 87 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 88 89 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 90 91 val memIO = if (params.isMemSchd) Some(new Bundle { 92 val lsqEnqIO = Flipped(new LsqEnqIO) 93 }) else None 94 val fromMem = if (params.isMemSchd) Some(new Bundle { 95 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 96 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 97 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 98 val stIssuePtr = Input(new SqPtr()) 99 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 100 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 101 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 102 val lqDeqPtr = Input(new LqPtr) 103 val sqDeqPtr = Input(new SqPtr) 104 // from lsq 105 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 106 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 107 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 108 }) else None 109 val toMem = if (params.isMemSchd) Some(new Bundle { 110 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 111 }) else None 112} 113 114abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 115 extends LazyModuleImp(wrapper) 116 with HasXSParameter 117{ 118 val io = IO(new SchedulerIO()) 119 120 // alias 121 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 122 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 123 private val schdType = params.schdType 124 125 // Modules 126 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 127 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 128 if (params.isIntSchd) { 129 dispatch2Iq.io.IQValidNumVec.get := io.IQValidNumVec 130 io.IQValidNumVec := MixedVecInit(issueQueues.map(_.io.validCntDeqVec)) 131 } 132 else io.IQValidNumVec := 0.U.asTypeOf(io.IQValidNumVec) 133 134 // valid count 135 dispatch2Iq.io.iqValidCnt := issueQueues.filter(_.params.StdCnt == 0).map(_.io.status.validCnt) 136 137 // BusyTable Modules 138 val intBusyTable = schdType match { 139 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 140 case _ => None 141 } 142 143 val vfBusyTable = schdType match { 144 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 145 case _ => None 146 } 147 148 dispatch2Iq.io match { case dp2iq => 149 dp2iq.redirect <> io.fromCtrlBlock.flush 150 dp2iq.in <> io.fromDispatch.uops 151 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 152 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 153 } 154 155 intBusyTable match { 156 case Some(bt) => 157 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 158 btAllocPregs.valid := dpAllocPregs.isInt 159 btAllocPregs.bits := dpAllocPregs.preg 160 } 161 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 162 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 163 wb.bits := io.intWriteBack(i).addr 164 } 165 bt.io.wakeUp := io.fromSchedulers.wakeupVec 166 bt.io.cancel := io.fromDataPath.cancelToBusyTable 167 bt.io.ldCancel := io.ldCancel 168 case None => 169 } 170 171 vfBusyTable match { 172 case Some(bt) => 173 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 174 btAllocPregs.valid := dpAllocPregs.isFp 175 btAllocPregs.bits := dpAllocPregs.preg 176 } 177 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 178 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 179 wb.bits := io.vfWriteBack(i).addr 180 } 181 bt.io.wakeUp := io.fromSchedulers.wakeupVec 182 bt.io.cancel := io.fromDataPath.cancelToBusyTable 183 bt.io.ldCancel := io.ldCancel 184 case None => 185 } 186 187 val wakeupFromIntWBVec = Wire(params.genIntWBWakeUpSinkValidBundle) 188 val wakeupFromVfWBVec = Wire(params.genVfWBWakeUpSinkValidBundle) 189 190 wakeupFromIntWBVec.zip(io.intWriteBack).foreach { case (sink, source) => 191 sink.valid := source.wen 192 sink.bits.rfWen := source.intWen 193 sink.bits.fpWen := source.fpWen 194 sink.bits.vecWen := source.vecWen 195 sink.bits.pdest := source.addr 196 } 197 198 wakeupFromVfWBVec.zip(io.vfWriteBack).foreach { case (sink, source) => 199 sink.valid := source.wen 200 sink.bits.rfWen := source.intWen 201 sink.bits.fpWen := source.fpWen 202 sink.bits.vecWen := source.vecWen 203 sink.bits.pdest := source.addr 204 } 205 206 // Connect bundles having the same wakeup source 207 issueQueues.zipWithIndex.foreach { case(iq, i) => 208 iq.io.wakeupFromIQ.foreach { wakeUp => 209 val wakeUpIn = iqWakeUpInMap(wakeUp.bits.exuIdx) 210 val exuIdx = wakeUp.bits.exuIdx 211 println(s"[Backend] Connect wakeup exuIdx ${exuIdx}") 212 connectSamePort(wakeUp,wakeUpIn) 213 backendParams.connectWakeup(exuIdx) 214 if (backendParams.isCopyPdest(exuIdx)) { 215 println(s"[Backend] exuIdx ${exuIdx} use pdestCopy ${backendParams.getCopyPdestIndex(exuIdx)}") 216 wakeUp.bits.pdest := wakeUpIn.bits.pdestCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 217 if (wakeUpIn.bits.rfWenCopy.nonEmpty) wakeUp.bits.rfWen := wakeUpIn.bits.rfWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 218 if (wakeUpIn.bits.fpWenCopy.nonEmpty) wakeUp.bits.fpWen := wakeUpIn.bits.fpWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 219 if (wakeUpIn.bits.vecWenCopy.nonEmpty) wakeUp.bits.vecWen := wakeUpIn.bits.vecWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 220 if (wakeUpIn.bits.loadDependencyCopy.nonEmpty) wakeUp.bits.loadDependency := wakeUpIn.bits.loadDependencyCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 221 } 222 if (iq.params.numIntSrc == 0) wakeUp.bits.rfWen := false.B 223 if (iq.params.numFpSrc == 0) wakeUp.bits.fpWen := false.B 224 if (iq.params.numVfSrc == 0) wakeUp.bits.vecWen := false.B 225 } 226 iq.io.og0Cancel := io.fromDataPath.og0Cancel 227 iq.io.og1Cancel := io.fromDataPath.og1Cancel 228 iq.io.ldCancel := io.ldCancel 229 } 230 231 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 232 issueQueues.flatMap(_.io.wakeupToIQ) 233 .map(x => (x.bits.exuIdx, x)) 234 .toMap 235 236 // Connect bundles having the same wakeup source 237 io.toSchedulers.wakeupVec.foreach { wakeUp => 238 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 239 } 240 241 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 242 toDpDy <> issueQueues(i).io.deqDelay 243 } 244 245 // Response 246 issueQueues.zipWithIndex.foreach { case (iq, i) => 247 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 248 og0Resp := io.fromDataPath(i)(j).og0resp 249 } 250 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 251 og1Resp := io.fromDataPath(i)(j).og1resp 252 } 253 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 254 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 255 finalIssueResp := io.loadFinalIssueResp(i)(j) 256 } else { 257 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 258 } 259 }) 260 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 261 if (io.memAddrIssueResp(i).isDefinedAt(j)) { 262 memAddrIssueResp := io.memAddrIssueResp(i)(j) 263 } else { 264 memAddrIssueResp := 0.U.asTypeOf(memAddrIssueResp) 265 } 266 }) 267 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 268 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 269 } 270 271 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 272 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 273 274 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 275 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 276} 277 278class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 279 extends SchedulerImpBase(wrapper) 280 with HasXSParameter 281{ 282// dontTouch(io.vfWbFuBusyTable) 283 println(s"[SchedulerArithImp] " + 284 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 285 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 286 287 issueQueues.zipWithIndex.foreach { case (iq, i) => 288 iq.io.flush <> io.fromCtrlBlock.flush 289 iq.io.enq <> dispatch2Iq.io.out(i) 290 val intWBIQ = params.schdType match { 291 case IntScheduler() => wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) 292 case VfScheduler() => wakeupFromVfWBVec 293 case _ => null 294 } 295 iq.io.wakeupFromWB.zip(intWBIQ).foreach{ case (sink, source) => sink := source} 296 } 297} 298 299// FIXME: Vector mem instructions may not be handled properly! 300class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 301 extends SchedulerImpBase(wrapper) 302 with HasXSParameter 303{ 304 println(s"[SchedulerMemImp] " + 305 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 306 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 307 308 val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ) 309 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 310 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 311 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 312 val vecMemIQs = issueQueues.filter(_.params.isVecMemIQ) 313 val (hyuIQs, hyuIQIdxs) = issueQueues.zipWithIndex.filter(_._1.params.HyuCnt > 0).unzip 314 315 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 316 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 317 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 318 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 319 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 320 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 321 322 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 323 324 private val loadWakeUp = issueQueues.filter(_.params.LdExuCnt > 0).map(_.asInstanceOf[IssueQueueMemAddrImp].io.memIO.get.loadWakeUp).flatten 325 require(loadWakeUp.length == io.fromMem.get.wakeup.length) 326 loadWakeUp.zip(io.fromMem.get.wakeup).foreach(x => x._1 := x._2) 327 328 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 329 iq.io.flush <> io.fromCtrlBlock.flush 330 iq.io.enq <> dispatch2Iq.io.out(i) 331 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 332 } 333 334 ldAddrIQs.zipWithIndex.foreach { 335 case (imp: IssueQueueMemAddrImp, i) => 336 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 337 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 338 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 339 case _ => 340 } 341 342 stAddrIQs.zipWithIndex.foreach { 343 case (imp: IssueQueueMemAddrImp, i) => 344 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 345 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 346 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 347 case _ => 348 } 349 350 hyuIQs.zip(hyuIQIdxs).foreach { 351 case (imp: IssueQueueMemAddrImp, idx) => 352 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 353 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 354 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 355 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 356 // TODO: refactor ditry code 357 imp.io.deqDelay(1).ready := false.B 358 io.toDataPathAfterDelay(idx)(1).valid := false.B 359 io.toDataPathAfterDelay(idx)(1).bits := 0.U.asTypeOf(io.toDataPathAfterDelay(idx)(1).bits) 360 case _ => 361 } 362 363 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 364 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 365 366 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 367 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 368 369 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 370 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 371 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 372 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 373 374 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 375 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 376 377 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 378 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 379 380 val d2IqStaOut = dispatch2Iq.io.out.zipWithIndex.filter(staIdxSeq contains _._2).unzip._1.flatten 381 d2IqStaOut.zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 382 val isAllReady = staIQ.ready && stdIQ.ready 383 dp.ready := isAllReady 384 staIQ.valid := dp.valid && isAllReady 385 stdIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 386 } 387 388 val d2IqHyaOut = dispatch2Iq.io.out.zipWithIndex.filter(hyaIdxSeq contains _._2).unzip._1.flatten 389 d2IqHyaOut.zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 390 val isAllReady = hyaIQ.ready && hydIQ.ready 391 dp.ready := isAllReady 392 hyaIQ.valid := dp.valid && isAllReady 393 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 394 } 395 396 stDataIQs.zipWithIndex.foreach { case (iq, i) => 397 iq.io.flush <> io.fromCtrlBlock.flush 398 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 399 } 400 401 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 402 stdIQEnq.bits := staIQEnq.bits 403 // Store data reuses store addr src(1) in dispatch2iq 404 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 405 // \ 406 // ---src*(1)--> [stdIQ] 407 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 408 // instead of dispatch2Iq.io.out(x).bits.src*(1) 409 val stdIdx = 1 410 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 411 stdIQEnq.bits.srcLoadDependency(0) := staIQEnq.bits.srcLoadDependency(1) 412 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 413 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 414 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 415 } 416 417 vecMemIQs.foreach { 418 case imp: IssueQueueVecMemImp => 419 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 420 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 421 // not used 422 imp.io.memIO.get.feedbackIO := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO) 423 // maybe not used 424 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 425 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 426 imp.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => imp.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 427 428 case _ => 429 } 430 431 val lsqEnqCtrl = Module(new LsqEnqCtrl) 432 433 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 434 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 435 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 436 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 437 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 438 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 439 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 440} 441