1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles 9import xiangshan.backend.datapath.DataConfig.VAddrData 10import xiangshan.backend.regfile.RfWritePortWithConfig 11import xiangshan.backend.rename.BusyTable 12import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 13import xiangshan.backend.Bundles.{DynInst, IssueQueueWakeUpBundle} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numIntWb 24 val numVfStateWrite = backendParams.numVfWb 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 // params alias 39 private val LoadQueueSize = VirtualLoadQueueSize 40 41 val fromTop = new Bundle { 42 val hartId = Input(UInt(8.W)) 43 } 44 val fromWbFuBusyTable = new Bundle{ 45 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 46 } 47 val toWbFuBusyTable = new Bundle{ 48 val intFuBusyTableWrite = MixedVec(params.issueBlockParams.map(x => x.genWbFuBusyTableWriteBundle)) 49 val vfFuBusyTableWrite = MixedVec(params.issueBlockParams.map(x => x.genWbFuBusyTableWriteBundle)) 50 } 51 val fromCtrlBlock = new Bundle { 52 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 53 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 54 val flush = Flipped(ValidIO(new Redirect)) 55 } 56 val fromDispatch = new Bundle { 57 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 58 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 59 } 60 val intWriteBack = MixedVec(Vec(backendParams.intPregParams.numWrite, 61 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 62 val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite, 63 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 64 val toDataPath: MixedVec[MixedVec[DecoupledIO[Bundles.IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 65 val fromDataPath: MixedVec[MixedVec[Bundles.OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 66 67 val memIO = if (params.isMemSchd) Some(new Bundle { 68 val lsqEnqIO = Flipped(new LsqEnqIO) 69 }) else None 70 val fromMem = if (params.isMemSchd) Some(new Bundle { 71 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 72 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 73 val stIssuePtr = Input(new SqPtr()) 74 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 75 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 76 // from lsq 77 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 78 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 79 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 80 }) else None 81 val toMem = if (params.isMemSchd) Some(new Bundle { 82 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 83 }) else None 84} 85 86abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 87 extends LazyModuleImp(wrapper) 88 with HasXSParameter 89{ 90 val io = IO(new SchedulerIO()) 91 92 // alias 93 private val schdType = params.schdType 94 private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0)) 95 private val numPregs = params.numPregs 96 97 // Modules 98 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 99 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 100 101 // BusyTable Modules 102 val intBusyTable = schdType match { 103 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite))) 104 case _ => None 105 } 106 107 val vfBusyTable = schdType match { 108 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite))) 109 case _ => None 110 } 111 112 dispatch2Iq.io match { case dp2iq => 113 dp2iq.redirect <> io.fromCtrlBlock.flush 114 dp2iq.in <> io.fromDispatch.uops 115 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 116 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 117 } 118 119 intBusyTable match { 120 case Some(bt) => 121 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 122 btAllocPregs.valid := dpAllocPregs.isInt 123 btAllocPregs.bits := dpAllocPregs.preg 124 } 125 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 126 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 127 wb.bits := io.intWriteBack(i).addr 128 } 129 case None => 130 } 131 132 vfBusyTable match { 133 case Some(bt) => 134 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 135 btAllocPregs.valid := dpAllocPregs.isFp 136 btAllocPregs.bits := dpAllocPregs.preg 137 } 138 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 139 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 140 wb.bits := io.vfWriteBack(i).addr 141 } 142 case None => 143 } 144 145 val wakeupFromWBVec = Wire(Vec(params.numWakeupFromWB, ValidIO(new IssueQueueWakeUpBundle(params.pregIdxWidth)))) 146 val writeback = params.schdType match { 147 case IntScheduler() => io.intWriteBack 148 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 149 case VfScheduler() => io.vfWriteBack 150 case _ => Seq() 151 } 152 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 153 sink.valid := source.wen 154 sink.bits.rfWen := source.intWen 155 sink.bits.fpWen := source.fpWen 156 sink.bits.vecWen := source.vecWen 157 sink.bits.pdest := source.addr 158 } 159 160 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 161 toDp <> issueQueues(i).io.deq 162 } 163} 164 165class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 166 extends SchedulerImpBase(wrapper) 167 with HasXSParameter 168{ 169// dontTouch(io.vfWbFuBusyTable) 170 println(s"[SchedulerArithImp] " + 171 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 172 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 173 174 issueQueues.zipWithIndex.foreach { case (iq, i) => 175 iq.io.flush <> io.fromCtrlBlock.flush 176 iq.io.enq <> dispatch2Iq.io.out(i) 177 iq.io.wakeup := wakeupFromWBVec 178 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 179 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 180 deqResp.bits.success := false.B 181 deqResp.bits.respType := RSFeedbackType.issueSuccess 182 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 183 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 184 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 185 186 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 187 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 188 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.respType := RSFeedbackType.issueSuccess 189 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 190 191 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 192 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 193 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).deqResp.bits.respType := RSFeedbackType.issueSuccess 194 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 195 } 196 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 197 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 198 og0Resp.bits.success := false.B // Todo: remove it 199 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 200 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 201 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 202 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 203 204 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 205 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 206 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 207 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 208 209 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 210 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 211 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 212 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 213 } 214 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 215 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 216 og1Resp.bits.success := false.B 217 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 218 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 219 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 220 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 221 222 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 223 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 224 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 225 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 226 227 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 228 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 229 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 230 io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 231 } 232 233 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 234 } 235 236 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 237 case imp: IssueQueueIntImp => imp.io.enqJmp 238 case _ => None 239 }.filter(_.nonEmpty).flatMap(_.get) 240 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 241 242 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 243 iqJmp.pc := pc 244 iqJmp.target := target 245 } 246} 247 248class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 249 extends SchedulerImpBase(wrapper) 250 with HasXSParameter 251{ 252 println(s"[SchedulerMemImp] " + 253 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 254 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 255 256 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 257 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 258 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 259 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 260 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 261 262 issueQueues.zipWithIndex.foreach { case (iq, i) => 263 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 264 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 265 deqResp.bits.success := false.B 266 deqResp.bits.respType := RSFeedbackType.issueSuccess 267 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 268 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 269 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 270 271 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 272 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 273 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.respType := RSFeedbackType.issueSuccess 274 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 275 } 276 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 277 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 278 og0Resp.bits.success := false.B // Todo: remove it 279 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 280 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 281 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 282 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 283 284 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 285 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 286 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 287 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 288 } 289 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 290 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 291 og1Resp.bits.success := false.B 292 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 293 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 294 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 295 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 296 297 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 298 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 299 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 300 io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 301 } 302 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 303 } 304 305 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 306 iq.io.flush <> io.fromCtrlBlock.flush 307 iq.io.enq <> dispatch2Iq.io.out(i) 308 iq.io.wakeup := wakeupFromWBVec 309 } 310 311 ldAddrIQs.foreach { 312 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 313 case _ => 314 } 315 316 stAddrIQs.foreach { 317 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 318 case _ => 319 } 320 321 dispatch2Iq.io.out(1).zip(stAddrIQs(0).io.enq).zip(stDataIQs(0).io.enq).foreach{ case((di, staIQ), stdIQ) => 322 val isAllReady = staIQ.ready && stdIQ.ready 323 di.ready := isAllReady 324 staIQ.valid := di.valid && isAllReady 325 stdIQ.valid := di.valid && isAllReady 326 } 327 328 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 329 s"should be equal to number of data IQs(${stDataIQs})") 330 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 331 stdIQ.io.flush <> io.fromCtrlBlock.flush 332 333 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 334 stdIQEnq.bits := staIQEnq.bits 335 // Store data reuses store addr src(1) in dispatch2iq 336 // [dispatch2iq] --src*------src*(0)--> [staIQ] 337 // \ 338 // ---src*(1)--> [stdIQ] 339 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 340 // instead of dispatch2Iq.io.out(x).bits.src*(1) 341 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 342 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 343 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 344 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 345 } 346 stdIQ.io.wakeup := wakeupFromWBVec 347 } 348 349 val lsqEnqCtrl = Module(new LsqEnqCtrl) 350 351 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 352 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 353 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 354 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 355 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 356 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 357 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 358} 359