1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.regfile.RfWritePortWithConfig 12import xiangshan.backend.rename.BusyTable 13import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 override def shouldBeInlined: Boolean = false 24 25 val numIntStateWrite = backendParams.numPregWb(IntData()) 26 val numVfStateWrite = backendParams.numPregWb(VecData()) 27 28 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 29 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 30 31 lazy val module: SchedulerImpBase = params.schdType match { 32 case IntScheduler() => new SchedulerArithImp(this)(params, p) 33 case MemScheduler() => new SchedulerMemImp(this)(params, p) 34 case VfScheduler() => new SchedulerArithImp(this)(params, p) 35 case _ => null 36 } 37} 38 39class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 40 // params alias 41 private val LoadQueueSize = VirtualLoadQueueSize 42 43 val fromTop = new Bundle { 44 val hartId = Input(UInt(8.W)) 45 } 46 val fromWbFuBusyTable = new Bundle{ 47 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 48 } 49 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 50 51 val fromCtrlBlock = new Bundle { 52 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 53 val flush = Flipped(ValidIO(new Redirect)) 54 } 55 val fromDispatch = new Bundle { 56 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 57 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 58 } 59 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 60 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 61 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 62 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 63 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 64 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 65 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 66 67 val fromSchedulers = new Bundle { 68 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 69 } 70 71 val toSchedulers = new Bundle { 72 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 73 } 74 75 val fromDataPath = new Bundle { 76 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 77 val og0Cancel = Input(ExuOH(backendParams.numExu)) 78 // Todo: remove this after no cancel signal from og1 79 val og1Cancel = Input(ExuOH(backendParams.numExu)) 80 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 81 // just be compatible to old code 82 def apply(i: Int)(j: Int) = resp(i)(j) 83 } 84 85 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 86 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 87 88 val ldCancel = Vec(backendParams.LduCnt, Flipped(new LoadCancelIO)) 89 90 val memIO = if (params.isMemSchd) Some(new Bundle { 91 val lsqEnqIO = Flipped(new LsqEnqIO) 92 }) else None 93 val fromMem = if (params.isMemSchd) Some(new Bundle { 94 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 95 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 96 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 97 val stIssuePtr = Input(new SqPtr()) 98 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 99 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 100 // from lsq 101 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 102 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 103 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 104 }) else None 105 val toMem = if (params.isMemSchd) Some(new Bundle { 106 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 107 }) else None 108} 109 110abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 111 extends LazyModuleImp(wrapper) 112 with HasXSParameter 113{ 114 val io = IO(new SchedulerIO()) 115 116 // alias 117 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 118 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 119 private val schdType = params.schdType 120 121 // Modules 122 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 123 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 124 125 // BusyTable Modules 126 val intBusyTable = schdType match { 127 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 128 case _ => None 129 } 130 131 val vfBusyTable = schdType match { 132 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 133 case _ => None 134 } 135 136 dispatch2Iq.io match { case dp2iq => 137 dp2iq.redirect <> io.fromCtrlBlock.flush 138 dp2iq.in <> io.fromDispatch.uops 139 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 140 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 141 } 142 143 intBusyTable match { 144 case Some(bt) => 145 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 146 btAllocPregs.valid := dpAllocPregs.isInt 147 btAllocPregs.bits := dpAllocPregs.preg 148 } 149 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 150 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 151 wb.bits := io.intWriteBack(i).addr 152 } 153 bt.io.wakeUp := io.fromSchedulers.wakeupVec 154 bt.io.cancel := io.fromDataPath.cancelToBusyTable 155 case None => 156 } 157 158 vfBusyTable match { 159 case Some(bt) => 160 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 161 btAllocPregs.valid := dpAllocPregs.isFp 162 btAllocPregs.bits := dpAllocPregs.preg 163 } 164 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 165 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 166 wb.bits := io.vfWriteBack(i).addr 167 } 168 bt.io.wakeUp := io.fromSchedulers.wakeupVec 169 bt.io.cancel := io.fromDataPath.cancelToBusyTable 170 case None => 171 } 172 173 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 174 val writeback = params.schdType match { 175 case IntScheduler() => io.intWriteBack 176 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 177 case VfScheduler() => io.vfWriteBack 178 case _ => Seq() 179 } 180 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 181 sink.valid := source.wen 182 sink.bits.rfWen := source.intWen 183 sink.bits.fpWen := source.fpWen 184 sink.bits.vecWen := source.vecWen 185 sink.bits.pdest := source.addr 186 } 187 188 // Connect bundles having the same wakeup source 189 issueQueues.zipWithIndex.foreach { case(iq, i) => 190 iq.io.wakeupFromIQ.foreach { wakeUp => 191 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 192 } 193 iq.io.og0Cancel := io.fromDataPath.og0Cancel 194 iq.io.og1Cancel := io.fromDataPath.og1Cancel 195 iq.io.ldCancel := io.ldCancel 196 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 197 } 198 199 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 200 issueQueues.flatMap(_.io.wakeupToIQ) 201 .map(x => (x.bits.exuIdx, x)) 202 .toMap 203 204 // Connect bundles having the same wakeup source 205 io.toSchedulers.wakeupVec.foreach { wakeUp => 206 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 207 } 208 209 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 210 toDp <> issueQueues(i).io.deq 211 } 212 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 213 toDpDy <> issueQueues(i).io.deqDelay 214 } 215 216 // Response 217 issueQueues.zipWithIndex.foreach { case (iq, i) => 218 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 219 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 220 deqResp.bits.respType := RSFeedbackType.issueSuccess 221 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 222 deqResp.bits.dataInvalidSqIdx := DontCare 223 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 224 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 225 } 226 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 227 og0Resp := io.fromDataPath(i)(j).og0resp 228 } 229 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 230 og1Resp := io.fromDataPath(i)(j).og1resp 231 } 232 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 233 finalIssueResp := io.loadFinalIssueResp(i)(j) 234 }) 235 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 236 memAddrIssueResp := io.memAddrIssueResp(i)(j) 237 }) 238 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 239 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 240 } 241 242 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 243 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 244 245 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 246 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 247} 248 249class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 250 extends SchedulerImpBase(wrapper) 251 with HasXSParameter 252{ 253// dontTouch(io.vfWbFuBusyTable) 254 println(s"[SchedulerArithImp] " + 255 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 256 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 257 258 issueQueues.zipWithIndex.foreach { case (iq, i) => 259 iq.io.flush <> io.fromCtrlBlock.flush 260 iq.io.enq <> dispatch2Iq.io.out(i) 261 iq.io.wakeupFromWB := wakeupFromWBVec 262 } 263} 264 265// FIXME: Vector mem instructions may not be handled properly! 266class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 267 extends SchedulerImpBase(wrapper) 268 with HasXSParameter 269{ 270 println(s"[SchedulerMemImp] " + 271 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 272 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 273 274 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 275 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 276 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 277 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 278 val hyuIQs = issueQueues.filter(iq => iq.params.HyuCnt > 0) 279 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 280 281 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 282 283 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 284 iq.io.flush <> io.fromCtrlBlock.flush 285 iq.io.enq <> dispatch2Iq.io.out(i) 286 iq.io.wakeupFromWB := wakeupFromWBVec 287 } 288 289 ldAddrIQs.foreach { 290 case imp: IssueQueueMemAddrImp => 291 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 292 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 293 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 294 case _ => 295 } 296 297 stAddrIQs.foreach { 298 case imp: IssueQueueMemAddrImp => 299 imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 300 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 301 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 302 case _ => 303 } 304 305 hyuIQs.foreach { 306 case imp: IssueQueueMemAddrImp => 307 imp.io.memIO.get.feedbackIO <> io.fromMem.get.hyuFeedback 308 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 309 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 310 case _ => 311 } 312 313 // TODO: Implement vstu 314 issueQueues.filter(iq => iq.params.VstuCnt > 0).foreach { 315 case imp: IssueQueueMemAddrImp => 316 imp.io.memIO.get.feedbackIO <> DontCare 317 imp.io.memIO.get.checkWait.stIssuePtr := DontCare 318 imp.io.memIO.get.checkWait.memWaitUpdateReq := DontCare 319 case _ => 320 } 321 322 // TODO: Implement vldu 323 issueQueues.filter(iq => iq.params.VlduCnt > 0).foreach { 324 case imp: IssueQueueMemAddrImp => 325 imp.io.memIO.get.feedbackIO <> DontCare 326 imp.io.memIO.get.checkWait.stIssuePtr := DontCare 327 imp.io.memIO.get.checkWait.memWaitUpdateReq := DontCare 328 case _ => 329 } 330 331 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 332 333 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 334 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 335 val isAllReady = staIQ.ready && stdIQ.ready 336 di.ready := isAllReady 337 staIQ.valid := di.valid && isAllReady 338 stdIQ.valid := di.valid && isAllReady 339 } 340 } 341 342 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 343 s"should be equal to number of data IQs(${stDataIQs})") 344 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 345 stdIQ.io.flush <> io.fromCtrlBlock.flush 346 347 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 348 stdIQEnq.bits := staIQEnq.bits 349 // Store data reuses store addr src(1) in dispatch2iq 350 // [dispatch2iq] --src*------src*(0)--> [staIQ] 351 // \ 352 // ---src*(1)--> [stdIQ] 353 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 354 // instead of dispatch2Iq.io.out(x).bits.src*(1) 355 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 356 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 357 stdIQEnq.bits.dataSource(0) := staIQEnq.bits.dataSource(1) 358 stdIQEnq.bits.l1ExuOH(0) := staIQEnq.bits.l1ExuOH(1) 359 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 360 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 361 } 362 stdIQ.io.wakeupFromWB := wakeupFromWBVec 363 } 364 365 val lsqEnqCtrl = Module(new LsqEnqCtrl) 366 367 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 368 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 369 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 370 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 371 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 372 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 373 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 374} 375