1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.regfile.RfWritePortWithConfig 12import xiangshan.backend.rename.BusyTable 13import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numPregWb(IntData()) 24 val numVfStateWrite = backendParams.numPregWb(VecData()) 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module: SchedulerImpBase = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 // params alias 39 private val LoadQueueSize = VirtualLoadQueueSize 40 41 val fromTop = new Bundle { 42 val hartId = Input(UInt(8.W)) 43 } 44 val fromWbFuBusyTable = new Bundle{ 45 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 46 } 47 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 48 49 val fromCtrlBlock = new Bundle { 50 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 51 val flush = Flipped(ValidIO(new Redirect)) 52 } 53 val fromDispatch = new Bundle { 54 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 55 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 56 } 57 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 58 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 59 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 60 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 61 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 62 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 63 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 64 65 val fromSchedulers = new Bundle { 66 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 67 } 68 69 val toSchedulers = new Bundle { 70 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 71 } 72 73 val fromDataPath = new Bundle { 74 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 75 val og0Cancel = Input(ExuVec(backendParams.numExu)) 76 // Todo: remove this after no cancel signal from og1 77 val og1Cancel = Input(ExuVec(backendParams.numExu)) 78 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 79 // just be compatible to old code 80 def apply(i: Int)(j: Int) = resp(i)(j) 81 } 82 83 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 84 85 val ldCancel = Vec(backendParams.LduCnt, Flipped(new LoadCancelIO)) 86 87 val memIO = if (params.isMemSchd) Some(new Bundle { 88 val lsqEnqIO = Flipped(new LsqEnqIO) 89 }) else None 90 val fromMem = if (params.isMemSchd) Some(new Bundle { 91 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 92 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 93 val stIssuePtr = Input(new SqPtr()) 94 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 95 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 96 // from lsq 97 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 98 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 99 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 100 }) else None 101 val toMem = if (params.isMemSchd) Some(new Bundle { 102 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 103 }) else None 104} 105 106abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 107 extends LazyModuleImp(wrapper) 108 with HasXSParameter 109{ 110 val io = IO(new SchedulerIO()) 111 112 // alias 113 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 114 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 115 private val schdType = params.schdType 116 117 // Modules 118 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 119 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 120 121 // BusyTable Modules 122 val intBusyTable = schdType match { 123 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 124 case _ => None 125 } 126 127 val vfBusyTable = schdType match { 128 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 129 case _ => None 130 } 131 132 dispatch2Iq.io match { case dp2iq => 133 dp2iq.redirect <> io.fromCtrlBlock.flush 134 dp2iq.in <> io.fromDispatch.uops 135 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 136 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 137 } 138 139 intBusyTable match { 140 case Some(bt) => 141 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 142 btAllocPregs.valid := dpAllocPregs.isInt 143 btAllocPregs.bits := dpAllocPregs.preg 144 } 145 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 146 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 147 wb.bits := io.intWriteBack(i).addr 148 } 149 bt.io.wakeUp := io.fromSchedulers.wakeupVec 150 bt.io.cancel := io.fromDataPath.cancelToBusyTable 151 case None => 152 } 153 154 vfBusyTable match { 155 case Some(bt) => 156 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 157 btAllocPregs.valid := dpAllocPregs.isFp 158 btAllocPregs.bits := dpAllocPregs.preg 159 } 160 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 161 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 162 wb.bits := io.vfWriteBack(i).addr 163 } 164 bt.io.wakeUp := io.fromSchedulers.wakeupVec 165 bt.io.cancel := io.fromDataPath.cancelToBusyTable 166 case None => 167 } 168 169 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 170 val writeback = params.schdType match { 171 case IntScheduler() => io.intWriteBack 172 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 173 case VfScheduler() => io.vfWriteBack 174 case _ => Seq() 175 } 176 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 177 sink.valid := source.wen 178 sink.bits.rfWen := source.intWen 179 sink.bits.fpWen := source.fpWen 180 sink.bits.vecWen := source.vecWen 181 sink.bits.pdest := source.addr 182 } 183 184 // Connect bundles having the same wakeup source 185 issueQueues.zipWithIndex.foreach { case(iq, i) => 186 iq.io.wakeupFromIQ.foreach { wakeUp => 187 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 188 } 189 iq.io.og0Cancel := io.fromDataPath.og0Cancel 190 iq.io.og1Cancel := io.fromDataPath.og1Cancel 191 iq.io.ldCancel := io.ldCancel 192 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 193 } 194 195 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 196 issueQueues.flatMap(_.io.wakeupToIQ) 197 .map(x => (x.bits.exuIdx, x)) 198 .toMap 199 200 // Connect bundles having the same wakeup source 201 io.toSchedulers.wakeupVec.foreach { wakeUp => 202 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 203 } 204 205 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 206 toDp <> issueQueues(i).io.deq 207 } 208 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 209 toDpDy <> issueQueues(i).io.deqDelay 210 } 211 212 // Response 213 issueQueues.zipWithIndex.foreach { case (iq, i) => 214 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 215 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 216 deqResp.bits.respType := RSFeedbackType.issueSuccess 217 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 218 deqResp.bits.dataInvalidSqIdx := DontCare 219 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 220 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 221 } 222 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 223 og0Resp := io.fromDataPath(i)(j).og0resp 224 } 225 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 226 og1Resp := io.fromDataPath(i)(j).og1resp 227 } 228 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 229 finalIssueResp := io.loadFinalIssueResp(i)(j) 230 }) 231 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 232 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 233 } 234 235 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 236 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 237 238 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 239 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 240} 241 242class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 243 extends SchedulerImpBase(wrapper) 244 with HasXSParameter 245{ 246// dontTouch(io.vfWbFuBusyTable) 247 println(s"[SchedulerArithImp] " + 248 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 249 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 250 251 issueQueues.zipWithIndex.foreach { case (iq, i) => 252 iq.io.flush <> io.fromCtrlBlock.flush 253 iq.io.enq <> dispatch2Iq.io.out(i) 254 iq.io.wakeupFromWB := wakeupFromWBVec 255 } 256} 257 258// FIXME: Vector mem instructions may not be handled properly! 259class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 260 extends SchedulerImpBase(wrapper) 261 with HasXSParameter 262{ 263 println(s"[SchedulerMemImp] " + 264 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 265 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 266 267 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 268 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 269 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 270 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 271 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 272 273 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 274 275 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 276 iq.io.flush <> io.fromCtrlBlock.flush 277 iq.io.enq <> dispatch2Iq.io.out(i) 278 iq.io.wakeupFromWB := wakeupFromWBVec 279 } 280 281 ldAddrIQs.foreach { 282 case imp: IssueQueueMemAddrImp => 283 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 284 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 285 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 286 case _ => 287 } 288 289 stAddrIQs.foreach { 290 case imp: IssueQueueMemAddrImp => 291 imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 292 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 293 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 294 case _ => 295 } 296 297 // TODO: Implement vstu 298 issueQueues.filter(iq => iq.params.VstuCnt > 0).foreach { 299 case imp: IssueQueueMemAddrImp => 300 imp.io.memIO.get.feedbackIO <> DontCare 301 imp.io.memIO.get.checkWait.stIssuePtr := DontCare 302 imp.io.memIO.get.checkWait.memWaitUpdateReq := DontCare 303 case _ => 304 } 305 306 // TODO: Implement vldu 307 issueQueues.filter(iq => iq.params.VlduCnt > 0).foreach { 308 case imp: IssueQueueMemAddrImp => 309 imp.io.memIO.get.feedbackIO <> DontCare 310 imp.io.memIO.get.checkWait.stIssuePtr := DontCare 311 imp.io.memIO.get.checkWait.memWaitUpdateReq := DontCare 312 case _ => 313 } 314 315 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 316 317 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 318 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 319 val isAllReady = staIQ.ready && stdIQ.ready 320 di.ready := isAllReady 321 staIQ.valid := di.valid && isAllReady 322 stdIQ.valid := di.valid && isAllReady 323 } 324 } 325 326 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 327 s"should be equal to number of data IQs(${stDataIQs})") 328 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 329 stdIQ.io.flush <> io.fromCtrlBlock.flush 330 331 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 332 stdIQEnq.bits := staIQEnq.bits 333 // Store data reuses store addr src(1) in dispatch2iq 334 // [dispatch2iq] --src*------src*(0)--> [staIQ] 335 // \ 336 // ---src*(1)--> [stdIQ] 337 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 338 // instead of dispatch2Iq.io.out(x).bits.src*(1) 339 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 340 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 341 stdIQEnq.bits.dataSource(0) := staIQEnq.bits.dataSource(1) 342 stdIQEnq.bits.l1ExuOH(0) := staIQEnq.bits.l1ExuOH(1) 343 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 344 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 345 } 346 stdIQ.io.wakeupFromWB := wakeupFromWBVec 347 } 348 349 val lsqEnqCtrl = Module(new LsqEnqCtrl) 350 351 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 352 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 353 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 354 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 355 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 356 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 357 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 358} 359