1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.regfile.RfWritePortWithConfig 12import xiangshan.backend.rename.BusyTable 13import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numPregWb(IntData()) 24 val numVfStateWrite = backendParams.numPregWb(VecData()) 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 // params alias 39 private val LoadQueueSize = VirtualLoadQueueSize 40 41 val fromTop = new Bundle { 42 val hartId = Input(UInt(8.W)) 43 } 44 val fromWbFuBusyTable = new Bundle{ 45 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 46 } 47 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 48 49 val fromCtrlBlock = new Bundle { 50 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 51 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 52 val flush = Flipped(ValidIO(new Redirect)) 53 } 54 val fromDispatch = new Bundle { 55 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 56 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 57 } 58 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 59 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 60 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 61 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 62 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 63 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 64 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 65 66 val fromSchedulers = new Bundle { 67 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 68 } 69 70 val toSchedulers = new Bundle { 71 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 72 } 73 74 val fromDataPath = new Bundle { 75 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 76 val og0Cancel = Input(ExuVec(backendParams.numExu)) 77 // Todo: remove this after no cancel signal from og1 78 val og1Cancel = Input(ExuVec(backendParams.numExu)) 79 // just be compatible to old code 80 def apply(i: Int)(j: Int) = resp(i)(j) 81 } 82 83 84 val memIO = if (params.isMemSchd) Some(new Bundle { 85 val lsqEnqIO = Flipped(new LsqEnqIO) 86 }) else None 87 val fromMem = if (params.isMemSchd) Some(new Bundle { 88 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 89 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 90 val stIssuePtr = Input(new SqPtr()) 91 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 92 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 93 // from lsq 94 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 95 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 96 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 97 }) else None 98 val toMem = if (params.isMemSchd) Some(new Bundle { 99 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 100 }) else None 101} 102 103abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 104 extends LazyModuleImp(wrapper) 105 with HasXSParameter 106{ 107 val io = IO(new SchedulerIO()) 108 109 // alias 110 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 111 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 112 private val schdType = params.schdType 113 114 // Modules 115 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 116 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 117 118 // BusyTable Modules 119 val intBusyTable = schdType match { 120 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs))) 121 case _ => None 122 } 123 124 val vfBusyTable = schdType match { 125 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs))) 126 case _ => None 127 } 128 129 dispatch2Iq.io match { case dp2iq => 130 dp2iq.redirect <> io.fromCtrlBlock.flush 131 dp2iq.in <> io.fromDispatch.uops 132 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 133 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 134 } 135 136 intBusyTable match { 137 case Some(bt) => 138 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 139 btAllocPregs.valid := dpAllocPregs.isInt 140 btAllocPregs.bits := dpAllocPregs.preg 141 } 142 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 143 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 144 wb.bits := io.intWriteBack(i).addr 145 } 146 case None => 147 } 148 149 vfBusyTable match { 150 case Some(bt) => 151 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 152 btAllocPregs.valid := dpAllocPregs.isFp 153 btAllocPregs.bits := dpAllocPregs.preg 154 } 155 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 156 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 157 wb.bits := io.vfWriteBack(i).addr 158 } 159 case None => 160 } 161 162 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 163 val writeback = params.schdType match { 164 case IntScheduler() => io.intWriteBack 165 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 166 case VfScheduler() => io.vfWriteBack 167 case _ => Seq() 168 } 169 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 170 sink.valid := source.wen 171 sink.bits.rfWen := source.intWen 172 sink.bits.fpWen := source.fpWen 173 sink.bits.vecWen := source.vecWen 174 sink.bits.pdest := source.addr 175 } 176 177 // Connect bundles having the same wakeup source 178 issueQueues.zipWithIndex.foreach { case(iq, i) => 179 iq.io.wakeupFromIQ.foreach { wakeUp => 180 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 181 } 182 iq.io.og0Cancel := io.fromDataPath.og0Cancel 183 iq.io.og1Cancel := io.fromDataPath.og1Cancel 184 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 185 } 186 187 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 188 issueQueues.flatMap(_.io.wakeupToIQ) 189 .map(x => (x.bits.exuIdx, x)) 190 .toMap 191 192 // Connect bundles having the same wakeup source 193 io.toSchedulers.wakeupVec.foreach { wakeUp => 194 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 195 } 196 197 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 198 toDp <> issueQueues(i).io.deq 199 } 200 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 201 toDpDy <> issueQueues(i).io.deqDelay 202 } 203 204 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 205 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 206 207 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 208 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 209} 210 211class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 212 extends SchedulerImpBase(wrapper) 213 with HasXSParameter 214{ 215// dontTouch(io.vfWbFuBusyTable) 216 println(s"[SchedulerArithImp] " + 217 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 218 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 219 220 issueQueues.zipWithIndex.foreach { case (iq, i) => 221 iq.io.flush <> io.fromCtrlBlock.flush 222 iq.io.enq <> dispatch2Iq.io.out(i) 223 iq.io.wakeupFromWB := wakeupFromWBVec 224 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 225 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 226 deqResp.bits.respType := RSFeedbackType.issueSuccess 227 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 228 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 229 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 230 231 } 232 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 233 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 234 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 235 og0Resp.bits.robIdx := io.fromDataPath(i)(j).og0resp.bits.robIdx 236 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 237 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 238 239 } 240 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 241 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 242 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 243 og1Resp.bits.robIdx := io.fromDataPath(i)(j).og1resp.bits.robIdx 244 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 245 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 246 247 } 248 249 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 250 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 251 } 252 253 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 254 case imp: IssueQueueIntImp => imp.io.enqJmp 255 case _ => None 256 }.filter(_.nonEmpty).flatMap(_.get) 257 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 258 259 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 260 iqJmp.pc := pc 261 iqJmp.target := target 262 } 263} 264 265class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 266 extends SchedulerImpBase(wrapper) 267 with HasXSParameter 268{ 269 println(s"[SchedulerMemImp] " + 270 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 271 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 272 273 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 274 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 275 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 276 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 277 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 278 279 issueQueues.zipWithIndex.foreach { case (iq, i) => 280 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 281 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 282 deqResp.bits.respType := RSFeedbackType.issueSuccess 283 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 284 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 285 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 286 287 } 288 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 289 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 290 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 291 og0Resp.bits.robIdx := io.fromDataPath(i)(j).og0resp.bits.robIdx 292 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 293 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 294 295 } 296 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 297 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 298 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 299 og1Resp.bits.robIdx := io.fromDataPath(i)(j).og1resp.bits.robIdx 300 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 301 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 302 303 } 304 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 305 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 306 } 307 308 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 309 iq.io.flush <> io.fromCtrlBlock.flush 310 iq.io.enq <> dispatch2Iq.io.out(i) 311 iq.io.wakeupFromWB := wakeupFromWBVec 312 } 313 314 ldAddrIQs.foreach { 315 case imp: IssueQueueMemAddrImp => 316 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 317 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 318 case _ => 319 } 320 321 stAddrIQs.foreach { 322 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 323 case _ => 324 } 325 326 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 327 328 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 329 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 330 val isAllReady = staIQ.ready && stdIQ.ready 331 di.ready := isAllReady 332 staIQ.valid := di.valid && isAllReady 333 stdIQ.valid := di.valid && isAllReady 334 } 335 } 336 337 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 338 s"should be equal to number of data IQs(${stDataIQs})") 339 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 340 stdIQ.io.flush <> io.fromCtrlBlock.flush 341 342 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 343 stdIQEnq.bits := staIQEnq.bits 344 // Store data reuses store addr src(1) in dispatch2iq 345 // [dispatch2iq] --src*------src*(0)--> [staIQ] 346 // \ 347 // ---src*(1)--> [stdIQ] 348 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 349 // instead of dispatch2Iq.io.out(x).bits.src*(1) 350 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 351 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 352 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 353 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 354 } 355 stdIQ.io.wakeupFromWB := wakeupFromWBVec 356 } 357 358 val lsqEnqCtrl = Module(new LsqEnqCtrl) 359 360 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 361 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 362 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 363 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 364 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 365 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 366 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 367} 368