1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.VAddrData 10import xiangshan.backend.regfile.RfWritePortWithConfig 11import xiangshan.backend.rename.BusyTable 12import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 13 14sealed trait SchedulerType 15 16case class IntScheduler() extends SchedulerType 17case class MemScheduler() extends SchedulerType 18case class VfScheduler() extends SchedulerType 19case class NoScheduler() extends SchedulerType 20 21class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 22 val numIntStateWrite = backendParams.numIntWb 23 val numVfStateWrite = backendParams.numVfWb 24 25 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 26 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 27 28 lazy val module = params.schdType match { 29 case IntScheduler() => new SchedulerArithImp(this)(params, p) 30 case MemScheduler() => new SchedulerMemImp(this)(params, p) 31 case VfScheduler() => new SchedulerArithImp(this)(params, p) 32 case _ => null 33 } 34} 35 36class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends Bundle { 37 // params alias 38 private val backendParams = params.backendParam 39 private val LoadQueueSize = p(XSCoreParamsKey).VirtualLoadQueueSize 40 private val RenameWidth = p(XSCoreParamsKey).RenameWidth 41 private val CommitWidth = p(XSCoreParamsKey).CommitWidth 42 private val EnsbufferWidth = p(XSCoreParamsKey).EnsbufferWidth 43 private val StoreQueueSize = p(XSCoreParamsKey).StoreQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 53 val fromCtrlBlock = new Bundle { 54 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 55 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 56 val flush = Flipped(ValidIO(new Redirect)) 57 } 58 val fromDispatch = new Bundle { 59 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 60 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 61 } 62 val intWriteBack = MixedVec(Vec(backendParams.intPregParams.numWrite, 63 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 64 val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite, 65 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 66 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 67 68 val fromSchedulers = new Bundle { 69 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 70 } 71 72 val toSchedulers = new Bundle { 73 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 74 } 75 76 val fromDataPath = new Bundle { 77 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 78 val og0Cancel = Input(ExuVec(backendParams.numExu)) 79 // Todo: remove this after no cancel signal from og1 80 val og1Cancel = Input(ExuVec(backendParams.numExu)) 81 // just be compatible to old code 82 def apply(i: Int)(j: Int) = resp(i)(j) 83 } 84 85 86 val memIO = if (params.isMemSchd) Some(new Bundle { 87 val lsqEnqIO = Flipped(new LsqEnqIO) 88 }) else None 89 val fromMem = if (params.isMemSchd) Some(new Bundle { 90 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 91 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 92 val stIssuePtr = Input(new SqPtr()) 93 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 94 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 95 // from lsq 96 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 97 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 98 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 99 }) else None 100 val toMem = if (params.isMemSchd) Some(new Bundle { 101 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 102 }) else None 103} 104 105abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 106 extends LazyModuleImp(wrapper) 107 with HasXSParameter 108{ 109 val io = IO(new SchedulerIO()) 110 111 // alias 112 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 113 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 114 private val schdType = params.schdType 115 private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0)) 116 private val numPregs = params.numPregs 117 118 // Modules 119 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 120 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 121 122 // BusyTable Modules 123 val intBusyTable = schdType match { 124 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite))) 125 case _ => None 126 } 127 128 val vfBusyTable = schdType match { 129 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite))) 130 case _ => None 131 } 132 133 dispatch2Iq.io match { case dp2iq => 134 dp2iq.redirect <> io.fromCtrlBlock.flush 135 dp2iq.in <> io.fromDispatch.uops 136 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 137 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 138 } 139 140 intBusyTable match { 141 case Some(bt) => 142 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 143 btAllocPregs.valid := dpAllocPregs.isInt 144 btAllocPregs.bits := dpAllocPregs.preg 145 } 146 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 147 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 148 wb.bits := io.intWriteBack(i).addr 149 } 150 case None => 151 } 152 153 vfBusyTable match { 154 case Some(bt) => 155 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 156 btAllocPregs.valid := dpAllocPregs.isFp 157 btAllocPregs.bits := dpAllocPregs.preg 158 } 159 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 160 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 161 wb.bits := io.vfWriteBack(i).addr 162 } 163 case None => 164 } 165 166 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 167 val writeback = params.schdType match { 168 case IntScheduler() => io.intWriteBack 169 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 170 case VfScheduler() => io.vfWriteBack 171 case _ => Seq() 172 } 173 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 174 sink.valid := source.wen 175 sink.bits.rfWen := source.intWen 176 sink.bits.fpWen := source.fpWen 177 sink.bits.vecWen := source.vecWen 178 sink.bits.pdest := source.addr 179 } 180 181 // Connect bundles having the same wakeup source 182 issueQueues.foreach { iq => 183 iq.io.wakeupFromIQ.foreach { wakeUp => 184 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 185 } 186 iq.io.og0Cancel := io.fromDataPath.og0Cancel 187 iq.io.og1Cancel := io.fromDataPath.og1Cancel 188 } 189 190 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 191 issueQueues.flatMap(_.io.wakeupToIQ) 192 .map(x => (x.bits.exuIdx, x)) 193 .toMap 194 195 // Connect bundles having the same wakeup source 196 io.toSchedulers.wakeupVec.foreach { wakeUp => 197 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 198 } 199 200 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 201 toDp <> issueQueues(i).io.deq 202 } 203 204 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 205 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 206 207 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 208 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 209} 210 211class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 212 extends SchedulerImpBase(wrapper) 213 with HasXSParameter 214{ 215// dontTouch(io.vfWbFuBusyTable) 216 println(s"[SchedulerArithImp] " + 217 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 218 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 219 220 issueQueues.zipWithIndex.foreach { case (iq, i) => 221 iq.io.flush <> io.fromCtrlBlock.flush 222 iq.io.enq <> dispatch2Iq.io.out(i) 223 iq.io.wakeupFromWB := wakeupFromWBVec 224 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 225 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 226 deqResp.bits.respType := RSFeedbackType.issueSuccess 227 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 228 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 229 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 230 231 } 232 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 233 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 234 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 235 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 236 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 237 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 238 239 } 240 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 241 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 242 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 243 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 244 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 245 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 246 247 } 248 249 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 250 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 251 } 252 253 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 254 case imp: IssueQueueIntImp => imp.io.enqJmp 255 case _ => None 256 }.filter(_.nonEmpty).flatMap(_.get) 257 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 258 259 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 260 iqJmp.pc := pc 261 iqJmp.target := target 262 } 263} 264 265class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 266 extends SchedulerImpBase(wrapper) 267 with HasXSParameter 268{ 269 println(s"[SchedulerMemImp] " + 270 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 271 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 272 273 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 274 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 275 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 276 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 277 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 278 279 issueQueues.zipWithIndex.foreach { case (iq, i) => 280 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 281 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 282 deqResp.bits.respType := RSFeedbackType.issueSuccess 283 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 284 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 285 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 286 287 } 288 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 289 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 290 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 291 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 292 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 293 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 294 295 } 296 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 297 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 298 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 299 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 300 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 301 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 302 303 } 304 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 305 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 306 } 307 308 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 309 iq.io.flush <> io.fromCtrlBlock.flush 310 iq.io.enq <> dispatch2Iq.io.out(i) 311 iq.io.wakeupFromWB := wakeupFromWBVec 312 } 313 314 ldAddrIQs.foreach { 315 case imp: IssueQueueMemAddrImp => 316 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 317 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 318 case _ => 319 } 320 321 stAddrIQs.foreach { 322 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 323 case _ => 324 } 325 326 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 327 328 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 329 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 330 val isAllReady = staIQ.ready && stdIQ.ready 331 di.ready := isAllReady 332 staIQ.valid := di.valid && isAllReady 333 stdIQ.valid := di.valid && isAllReady 334 } 335 } 336 337 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 338 s"should be equal to number of data IQs(${stDataIQs})") 339 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 340 stdIQ.io.flush <> io.fromCtrlBlock.flush 341 342 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 343 stdIQEnq.bits := staIQEnq.bits 344 // Store data reuses store addr src(1) in dispatch2iq 345 // [dispatch2iq] --src*------src*(0)--> [staIQ] 346 // \ 347 // ---src*(1)--> [stdIQ] 348 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 349 // instead of dispatch2Iq.io.out(x).bits.src*(1) 350 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 351 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 352 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 353 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 354 } 355 stdIQ.io.wakeupFromWB := wakeupFromWBVec 356 } 357 358 val lsqEnqCtrl = Module(new LsqEnqCtrl) 359 360 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 361 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 362 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 363 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 364 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 365 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 366 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 367} 368