1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.VAddrData 10import xiangshan.backend.regfile.RfWritePortWithConfig 11import xiangshan.backend.rename.BusyTable 12import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 13 14sealed trait SchedulerType 15 16case class IntScheduler() extends SchedulerType 17case class MemScheduler() extends SchedulerType 18case class VfScheduler() extends SchedulerType 19case class NoScheduler() extends SchedulerType 20 21class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 22 val numIntStateWrite = backendParams.numIntWb 23 val numVfStateWrite = backendParams.numVfWb 24 25 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 26 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 27 28 lazy val module = params.schdType match { 29 case IntScheduler() => new SchedulerArithImp(this)(params, p) 30 case MemScheduler() => new SchedulerMemImp(this)(params, p) 31 case VfScheduler() => new SchedulerArithImp(this)(params, p) 32 case _ => null 33 } 34} 35 36class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends Bundle { 37 // params alias 38 private val backendParams = params.backendParam 39 private val LoadQueueSize = p(XSCoreParamsKey).VirtualLoadQueueSize 40 private val RenameWidth = p(XSCoreParamsKey).RenameWidth 41 private val CommitWidth = p(XSCoreParamsKey).CommitWidth 42 private val EnsbufferWidth = p(XSCoreParamsKey).EnsbufferWidth 43 private val StoreQueueSize = p(XSCoreParamsKey).StoreQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 53 val fromCtrlBlock = new Bundle { 54 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 55 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 56 val flush = Flipped(ValidIO(new Redirect)) 57 } 58 val fromDispatch = new Bundle { 59 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 60 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 61 } 62 val intWriteBack = MixedVec(Vec(backendParams.intPregParams.numWrite, 63 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 64 val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite, 65 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 66 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 67 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 68 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 69 70 val fromSchedulers = new Bundle { 71 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 72 } 73 74 val toSchedulers = new Bundle { 75 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 76 } 77 78 val fromDataPath = new Bundle { 79 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 80 val og0Cancel = Input(ExuVec(backendParams.numExu)) 81 // Todo: remove this after no cancel signal from og1 82 val og1Cancel = Input(ExuVec(backendParams.numExu)) 83 // just be compatible to old code 84 def apply(i: Int)(j: Int) = resp(i)(j) 85 } 86 87 88 val memIO = if (params.isMemSchd) Some(new Bundle { 89 val lsqEnqIO = Flipped(new LsqEnqIO) 90 }) else None 91 val fromMem = if (params.isMemSchd) Some(new Bundle { 92 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 93 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 94 val stIssuePtr = Input(new SqPtr()) 95 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 96 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 97 // from lsq 98 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 99 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 100 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 101 }) else None 102 val toMem = if (params.isMemSchd) Some(new Bundle { 103 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 104 }) else None 105} 106 107abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 108 extends LazyModuleImp(wrapper) 109 with HasXSParameter 110{ 111 val io = IO(new SchedulerIO()) 112 113 // alias 114 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 115 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 116 private val schdType = params.schdType 117 private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0)) 118 private val numPregs = params.numPregs 119 120 // Modules 121 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 122 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 123 124 // BusyTable Modules 125 val intBusyTable = schdType match { 126 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite))) 127 case _ => None 128 } 129 130 val vfBusyTable = schdType match { 131 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite))) 132 case _ => None 133 } 134 135 dispatch2Iq.io match { case dp2iq => 136 dp2iq.redirect <> io.fromCtrlBlock.flush 137 dp2iq.in <> io.fromDispatch.uops 138 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 139 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 140 } 141 142 intBusyTable match { 143 case Some(bt) => 144 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 145 btAllocPregs.valid := dpAllocPregs.isInt 146 btAllocPregs.bits := dpAllocPregs.preg 147 } 148 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 149 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 150 wb.bits := io.intWriteBack(i).addr 151 } 152 case None => 153 } 154 155 vfBusyTable match { 156 case Some(bt) => 157 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 158 btAllocPregs.valid := dpAllocPregs.isFp 159 btAllocPregs.bits := dpAllocPregs.preg 160 } 161 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 162 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 163 wb.bits := io.vfWriteBack(i).addr 164 } 165 case None => 166 } 167 168 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 169 val writeback = params.schdType match { 170 case IntScheduler() => io.intWriteBack 171 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 172 case VfScheduler() => io.vfWriteBack 173 case _ => Seq() 174 } 175 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 176 sink.valid := source.wen 177 sink.bits.rfWen := source.intWen 178 sink.bits.fpWen := source.fpWen 179 sink.bits.vecWen := source.vecWen 180 sink.bits.pdest := source.addr 181 } 182 183 // Connect bundles having the same wakeup source 184 issueQueues.zipWithIndex.foreach { case(iq, i) => 185 iq.io.wakeupFromIQ.foreach { wakeUp => 186 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 187 } 188 iq.io.og0Cancel := io.fromDataPath.og0Cancel 189 iq.io.og1Cancel := io.fromDataPath.og1Cancel 190 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 191 } 192 193 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 194 issueQueues.flatMap(_.io.wakeupToIQ) 195 .map(x => (x.bits.exuIdx, x)) 196 .toMap 197 198 // Connect bundles having the same wakeup source 199 io.toSchedulers.wakeupVec.foreach { wakeUp => 200 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 201 } 202 203 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 204 toDp <> issueQueues(i).io.deq 205 } 206 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 207 toDpDy <> issueQueues(i).io.deqDelay 208 } 209 210 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 211 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 212 213 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 214 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 215} 216 217class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 218 extends SchedulerImpBase(wrapper) 219 with HasXSParameter 220{ 221// dontTouch(io.vfWbFuBusyTable) 222 println(s"[SchedulerArithImp] " + 223 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 224 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 225 226 issueQueues.zipWithIndex.foreach { case (iq, i) => 227 iq.io.flush <> io.fromCtrlBlock.flush 228 iq.io.enq <> dispatch2Iq.io.out(i) 229 iq.io.wakeupFromWB := wakeupFromWBVec 230 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 231 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 232 deqResp.bits.respType := RSFeedbackType.issueSuccess 233 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 234 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 235 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 236 237 } 238 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 239 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 240 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 241 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 242 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 243 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 244 245 } 246 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 247 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 248 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 249 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 250 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 251 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 252 253 } 254 255 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 256 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 257 } 258 259 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 260 case imp: IssueQueueIntImp => imp.io.enqJmp 261 case _ => None 262 }.filter(_.nonEmpty).flatMap(_.get) 263 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 264 265 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 266 iqJmp.pc := pc 267 iqJmp.target := target 268 } 269} 270 271class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 272 extends SchedulerImpBase(wrapper) 273 with HasXSParameter 274{ 275 println(s"[SchedulerMemImp] " + 276 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 277 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 278 279 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 280 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 281 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 282 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 283 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 284 285 issueQueues.zipWithIndex.foreach { case (iq, i) => 286 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 287 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 288 deqResp.bits.respType := RSFeedbackType.issueSuccess 289 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 290 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 291 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 292 293 } 294 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 295 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 296 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 297 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 298 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 299 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 300 301 } 302 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 303 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 304 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 305 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 306 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 307 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 308 309 } 310 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 311 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 312 } 313 314 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 315 iq.io.flush <> io.fromCtrlBlock.flush 316 iq.io.enq <> dispatch2Iq.io.out(i) 317 iq.io.wakeupFromWB := wakeupFromWBVec 318 } 319 320 ldAddrIQs.foreach { 321 case imp: IssueQueueMemAddrImp => 322 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 323 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 324 case _ => 325 } 326 327 stAddrIQs.foreach { 328 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 329 case _ => 330 } 331 332 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 333 334 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 335 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 336 val isAllReady = staIQ.ready && stdIQ.ready 337 di.ready := isAllReady 338 staIQ.valid := di.valid && isAllReady 339 stdIQ.valid := di.valid && isAllReady 340 } 341 } 342 343 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 344 s"should be equal to number of data IQs(${stDataIQs})") 345 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 346 stdIQ.io.flush <> io.fromCtrlBlock.flush 347 348 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 349 stdIQEnq.bits := staIQEnq.bits 350 // Store data reuses store addr src(1) in dispatch2iq 351 // [dispatch2iq] --src*------src*(0)--> [staIQ] 352 // \ 353 // ---src*(1)--> [stdIQ] 354 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 355 // instead of dispatch2Iq.io.out(x).bits.src*(1) 356 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 357 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 358 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 359 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 360 } 361 stdIQ.io.wakeupFromWB := wakeupFromWBVec 362 } 363 364 val lsqEnqCtrl = Module(new LsqEnqCtrl) 365 366 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 367 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 368 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 369 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 370 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 371 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 372 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 373} 374