1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.regfile.RfWritePortWithConfig 14import xiangshan.backend.rename.BusyTable 15import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 16 17sealed trait SchedulerType 18 19case class IntScheduler() extends SchedulerType 20case class MemScheduler() extends SchedulerType 21case class VfScheduler() extends SchedulerType 22case class NoScheduler() extends SchedulerType 23 24class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 25 override def shouldBeInlined: Boolean = false 26 27 val numIntStateWrite = backendParams.numPregWb(IntData()) 28 val numVfStateWrite = backendParams.numPregWb(VecData()) 29 30 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 31 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 32 33 lazy val module: SchedulerImpBase = params.schdType match { 34 case IntScheduler() => new SchedulerArithImp(this)(params, p) 35 case MemScheduler() => new SchedulerMemImp(this)(params, p) 36 case VfScheduler() => new SchedulerArithImp(this)(params, p) 37 case _ => null 38 } 39} 40 41class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 42 // params alias 43 private val LoadQueueSize = VirtualLoadQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 53 val fromCtrlBlock = new Bundle { 54 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 55 val flush = Flipped(ValidIO(new Redirect)) 56 } 57 val fromDispatch = new Bundle { 58 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 59 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 60 } 61 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 62 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 63 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 64 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 65 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 66 67 val fromSchedulers = new Bundle { 68 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 69 } 70 71 val toSchedulers = new Bundle { 72 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 73 } 74 75 val fromDataPath = new Bundle { 76 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 77 val og0Cancel = Input(ExuOH(backendParams.numExu)) 78 // Todo: remove this after no cancel signal from og1 79 val og1Cancel = Input(ExuOH(backendParams.numExu)) 80 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 81 // just be compatible to old code 82 def apply(i: Int)(j: Int) = resp(i)(j) 83 } 84 85 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 86 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 87 88 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 89 90 val memIO = if (params.isMemSchd) Some(new Bundle { 91 val lsqEnqIO = Flipped(new LsqEnqIO) 92 }) else None 93 val fromMem = if (params.isMemSchd) Some(new Bundle { 94 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 95 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 96 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 97 val stIssuePtr = Input(new SqPtr()) 98 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 99 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 100 val wakeup = Vec(params.LdExuCnt /* + params.HyuCnt */, Flipped(Valid(new DynInst))) 101 val lqDeqPtr = Input(new LqPtr) 102 val sqDeqPtr = Input(new SqPtr) 103 // from lsq 104 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 105 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 106 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 107 }) else None 108 val toMem = if (params.isMemSchd) Some(new Bundle { 109 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 110 }) else None 111} 112 113abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 114 extends LazyModuleImp(wrapper) 115 with HasXSParameter 116{ 117 val io = IO(new SchedulerIO()) 118 119 // alias 120 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 121 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 122 private val schdType = params.schdType 123 124 // Modules 125 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 126 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 127 128 // valid count 129 dispatch2Iq.io.iqValidCnt := issueQueues.filter(_.params.StdCnt == 0).map(_.io.status.validCnt) 130 131 // BusyTable Modules 132 val intBusyTable = schdType match { 133 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 134 case _ => None 135 } 136 137 val vfBusyTable = schdType match { 138 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 139 case _ => None 140 } 141 142 dispatch2Iq.io match { case dp2iq => 143 dp2iq.redirect <> io.fromCtrlBlock.flush 144 dp2iq.in <> io.fromDispatch.uops 145 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 146 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 147 } 148 149 intBusyTable match { 150 case Some(bt) => 151 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 152 btAllocPregs.valid := dpAllocPregs.isInt 153 btAllocPregs.bits := dpAllocPregs.preg 154 } 155 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 156 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 157 wb.bits := io.intWriteBack(i).addr 158 } 159 bt.io.wakeUp := io.fromSchedulers.wakeupVec 160 bt.io.cancel := io.fromDataPath.cancelToBusyTable 161 bt.io.ldCancel := io.ldCancel 162 case None => 163 } 164 165 vfBusyTable match { 166 case Some(bt) => 167 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 168 btAllocPregs.valid := dpAllocPregs.isFp 169 btAllocPregs.bits := dpAllocPregs.preg 170 } 171 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 172 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 173 wb.bits := io.vfWriteBack(i).addr 174 } 175 bt.io.wakeUp := io.fromSchedulers.wakeupVec 176 bt.io.cancel := io.fromDataPath.cancelToBusyTable 177 bt.io.ldCancel := io.ldCancel 178 case None => 179 } 180 181 val wakeupFromIntWBVec = Wire(params.genIntWBWakeUpSinkValidBundle) 182 val wakeupFromVfWBVec = Wire(params.genVfWBWakeUpSinkValidBundle) 183 184 wakeupFromIntWBVec.zip(io.intWriteBack).foreach { case (sink, source) => 185 sink.valid := source.wen 186 sink.bits.rfWen := source.intWen 187 sink.bits.fpWen := source.fpWen 188 sink.bits.vecWen := source.vecWen 189 sink.bits.pdest := source.addr 190 } 191 192 wakeupFromVfWBVec.zip(io.vfWriteBack).foreach { case (sink, source) => 193 sink.valid := source.wen 194 sink.bits.rfWen := source.intWen 195 sink.bits.fpWen := source.fpWen 196 sink.bits.vecWen := source.vecWen 197 sink.bits.pdest := source.addr 198 } 199 200 // Connect bundles having the same wakeup source 201 issueQueues.zipWithIndex.foreach { case(iq, i) => 202 iq.io.wakeupFromIQ.foreach { wakeUp => 203 val wakeUpIn = iqWakeUpInMap(wakeUp.bits.exuIdx) 204 val exuIdx = wakeUp.bits.exuIdx 205 println(s"[Backend] Connect wakeup exuIdx ${exuIdx}") 206 connectSamePort(wakeUp,wakeUpIn) 207 backendParams.connectWakeup(exuIdx) 208 if (backendParams.isCopyPdest(exuIdx)) { 209 println(s"[Backend] exuIdx ${exuIdx} use pdestCopy ${backendParams.getCopyPdestIndex(exuIdx)}") 210 wakeUp.bits.pdest := wakeUpIn.bits.pdestCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 211 if (wakeUpIn.bits.rfWenCopy.nonEmpty) wakeUp.bits.rfWen := wakeUpIn.bits.rfWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 212 if (wakeUpIn.bits.fpWenCopy.nonEmpty) wakeUp.bits.fpWen := wakeUpIn.bits.fpWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 213 if (wakeUpIn.bits.vecWenCopy.nonEmpty) wakeUp.bits.vecWen := wakeUpIn.bits.vecWenCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 214 if (wakeUpIn.bits.loadDependencyCopy.nonEmpty) wakeUp.bits.loadDependency := wakeUpIn.bits.loadDependencyCopy.get(backendParams.getCopyPdestIndex(exuIdx)) 215 } 216 if (iq.params.numIntSrc == 0) wakeUp.bits.rfWen := false.B 217 if (iq.params.numFpSrc == 0) wakeUp.bits.fpWen := false.B 218 if (iq.params.numVfSrc == 0) wakeUp.bits.vecWen := false.B 219 } 220 iq.io.og0Cancel := io.fromDataPath.og0Cancel 221 iq.io.og1Cancel := io.fromDataPath.og1Cancel 222 iq.io.ldCancel := io.ldCancel 223 } 224 225 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 226 issueQueues.flatMap(_.io.wakeupToIQ) 227 .map(x => (x.bits.exuIdx, x)) 228 .toMap 229 230 // Connect bundles having the same wakeup source 231 io.toSchedulers.wakeupVec.foreach { wakeUp => 232 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 233 } 234 235 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 236 toDpDy <> issueQueues(i).io.deqDelay 237 } 238 239 // Response 240 issueQueues.zipWithIndex.foreach { case (iq, i) => 241 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 242 og0Resp := io.fromDataPath(i)(j).og0resp 243 } 244 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 245 og1Resp := io.fromDataPath(i)(j).og1resp 246 } 247 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 248 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 249 finalIssueResp := io.loadFinalIssueResp(i)(j) 250 } else { 251 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 252 } 253 }) 254 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 255 if (io.memAddrIssueResp(i).isDefinedAt(j)) { 256 memAddrIssueResp := io.memAddrIssueResp(i)(j) 257 } else { 258 memAddrIssueResp := 0.U.asTypeOf(memAddrIssueResp) 259 } 260 }) 261 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 262 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 263 } 264 265 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 266 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 267 268 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 269 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 270} 271 272class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 273 extends SchedulerImpBase(wrapper) 274 with HasXSParameter 275{ 276// dontTouch(io.vfWbFuBusyTable) 277 println(s"[SchedulerArithImp] " + 278 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 279 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 280 281 issueQueues.zipWithIndex.foreach { case (iq, i) => 282 iq.io.flush <> io.fromCtrlBlock.flush 283 iq.io.enq <> dispatch2Iq.io.out(i) 284 val intWBIQ = params.schdType match { 285 case IntScheduler() => wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) 286 case VfScheduler() => wakeupFromVfWBVec 287 case _ => null 288 } 289 iq.io.wakeupFromWB.zip(intWBIQ).foreach{ case (sink, source) => sink := source} 290 } 291} 292 293// FIXME: Vector mem instructions may not be handled properly! 294class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 295 extends SchedulerImpBase(wrapper) 296 with HasXSParameter 297{ 298 println(s"[SchedulerMemImp] " + 299 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 300 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 301 302 val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ) 303 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0 || iq.params.VstaCnt > 0) // included in memAddrIQs 304 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0 || iq.params.VlduCnt > 0) 305 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0 || iq.params.VstdCnt > 0) 306 val vecMemIQs = issueQueues.filter(_.params.isVecMemIQ) 307 val (hyuIQs, hyuIQIdxs) = issueQueues.zipWithIndex.filter(_._1.params.HyuCnt > 0).unzip 308 309 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 310 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 311 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 312 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 313 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 314 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 315 316 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 317 318 private val loadWakeUp = issueQueues.filter(_.params.StdCnt == 0).map(_.asInstanceOf[IssueQueueMemAddrImp].io.memIO.get.loadWakeUp).flatten 319 require(loadWakeUp.length == io.fromMem.get.wakeup.length) 320 loadWakeUp.zip(io.fromMem.get.wakeup).foreach(x => x._1 := x._2) 321 322 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 323 iq.io.flush <> io.fromCtrlBlock.flush 324 iq.io.enq <> dispatch2Iq.io.out(i) 325 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1) ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 326 } 327 328 ldAddrIQs.zipWithIndex.foreach { 329 case (imp: IssueQueueMemAddrImp, i) => 330 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 331 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 332 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 333 case _ => 334 } 335 336 stAddrIQs.zipWithIndex.foreach { 337 case (imp: IssueQueueMemAddrImp, i) => 338 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 339 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 340 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 341 case _ => 342 } 343 344 hyuIQs.zip(hyuIQIdxs).foreach { 345 case (imp: IssueQueueMemAddrImp, idx) => 346 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 347 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 348 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 349 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 350 // TODO: refactor ditry code 351 imp.io.deqDelay(1).ready := false.B 352 io.toDataPathAfterDelay(idx)(1).valid := false.B 353 io.toDataPathAfterDelay(idx)(1).bits := 0.U.asTypeOf(io.toDataPathAfterDelay(idx)(1).bits) 354 case _ => 355 } 356 357 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 358 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 359 360 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 361 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 362 363 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 364 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 365 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 366 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 367 368 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 369 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 370 371 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 372 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 373 374 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 375 dispatch2Iq.io.out(idxInSchBlk).zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 376 val isAllReady = staIQ.ready && stdIQ.ready 377 dp.ready := isAllReady 378 staIQ.valid := dp.valid && isAllReady 379 stdIQ.valid := dp.valid && isAllReady && FuType.isStore(dp.bits.fuType) 380 } 381 } 382 383 for ((idxInSchBlk, i) <- hyaIdxSeq.zipWithIndex) { 384 dispatch2Iq.io.out(idxInSchBlk).zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 385 val isAllReady = hyaIQ.ready && hydIQ.ready 386 dp.ready := isAllReady 387 hyaIQ.valid := dp.valid && isAllReady 388 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 389 } 390 } 391 392 stDataIQs.zipWithIndex.foreach { case (iq, i) => 393 iq.io.flush <> io.fromCtrlBlock.flush 394 iq.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => iq.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 395 } 396 397 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 398 stdIQEnq.bits := staIQEnq.bits 399 // Store data reuses store addr src(1) in dispatch2iq 400 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 401 // \ 402 // ---src*(1)--> [stdIQ] 403 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 404 // instead of dispatch2Iq.io.out(x).bits.src*(1) 405 val stdIdx = 1 406 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 407 stdIQEnq.bits.srcLoadDependency(0) := staIQEnq.bits.srcLoadDependency(1) 408 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 409 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 410 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 411 } 412 413 vecMemIQs.foreach { 414 case imp: IssueQueueVecMemImp => 415 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 416 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 417 // not used 418 imp.io.memIO.get.feedbackIO := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO) 419 // maybe not used 420 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 421 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 422 imp.io.wakeupFromWB.zip(wakeupFromIntWBVec.zipWithIndex.filter(x => imp.params.needWakeupFromIntWBPort.keys.toSeq.contains(x._2)).map(_._1).toSeq ++ wakeupFromVfWBVec).foreach{ case (sink, source) => sink := source} 423 424 case _ => 425 } 426 427 val lsqEnqCtrl = Module(new LsqEnqCtrl) 428 429 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 430 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 431 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 432 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 433 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 434 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 435 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 436} 437