1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.regfile.RfWritePortWithConfig 12import xiangshan.backend.rename.BusyTable 13import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numPregWb(IntData()) 24 val numVfStateWrite = backendParams.numPregWb(VecData()) 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends Bundle { 38 // params alias 39 private val backendParams = params.backendParam 40 private val LoadQueueSize = p(XSCoreParamsKey).VirtualLoadQueueSize 41 private val RenameWidth = p(XSCoreParamsKey).RenameWidth 42 private val CommitWidth = p(XSCoreParamsKey).CommitWidth 43 private val EnsbufferWidth = p(XSCoreParamsKey).EnsbufferWidth 44 private val StoreQueueSize = p(XSCoreParamsKey).StoreQueueSize 45 46 val fromTop = new Bundle { 47 val hartId = Input(UInt(8.W)) 48 } 49 val fromWbFuBusyTable = new Bundle{ 50 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 51 } 52 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 53 54 val fromCtrlBlock = new Bundle { 55 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 56 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 57 val flush = Flipped(ValidIO(new Redirect)) 58 } 59 val fromDispatch = new Bundle { 60 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 61 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 62 } 63 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 64 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 65 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 66 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 67 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 68 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 69 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 70 71 val fromSchedulers = new Bundle { 72 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 73 } 74 75 val toSchedulers = new Bundle { 76 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 77 } 78 79 val fromDataPath = new Bundle { 80 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 81 val og0Cancel = Input(ExuVec(backendParams.numExu)) 82 // Todo: remove this after no cancel signal from og1 83 val og1Cancel = Input(ExuVec(backendParams.numExu)) 84 // just be compatible to old code 85 def apply(i: Int)(j: Int) = resp(i)(j) 86 } 87 88 89 val memIO = if (params.isMemSchd) Some(new Bundle { 90 val lsqEnqIO = Flipped(new LsqEnqIO) 91 }) else None 92 val fromMem = if (params.isMemSchd) Some(new Bundle { 93 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 94 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 95 val stIssuePtr = Input(new SqPtr()) 96 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 97 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 98 // from lsq 99 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 100 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 101 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 102 }) else None 103 val toMem = if (params.isMemSchd) Some(new Bundle { 104 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 105 }) else None 106} 107 108abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 109 extends LazyModuleImp(wrapper) 110 with HasXSParameter 111{ 112 val io = IO(new SchedulerIO()) 113 114 // alias 115 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 116 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 117 private val schdType = params.schdType 118 119 // Modules 120 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 121 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 122 123 // BusyTable Modules 124 val intBusyTable = schdType match { 125 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs))) 126 case _ => None 127 } 128 129 val vfBusyTable = schdType match { 130 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs))) 131 case _ => None 132 } 133 134 dispatch2Iq.io match { case dp2iq => 135 dp2iq.redirect <> io.fromCtrlBlock.flush 136 dp2iq.in <> io.fromDispatch.uops 137 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 138 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 139 } 140 141 intBusyTable match { 142 case Some(bt) => 143 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 144 btAllocPregs.valid := dpAllocPregs.isInt 145 btAllocPregs.bits := dpAllocPregs.preg 146 } 147 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 148 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 149 wb.bits := io.intWriteBack(i).addr 150 } 151 case None => 152 } 153 154 vfBusyTable match { 155 case Some(bt) => 156 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 157 btAllocPregs.valid := dpAllocPregs.isFp 158 btAllocPregs.bits := dpAllocPregs.preg 159 } 160 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 161 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 162 wb.bits := io.vfWriteBack(i).addr 163 } 164 case None => 165 } 166 167 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 168 val writeback = params.schdType match { 169 case IntScheduler() => io.intWriteBack 170 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 171 case VfScheduler() => io.vfWriteBack 172 case _ => Seq() 173 } 174 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 175 sink.valid := source.wen 176 sink.bits.rfWen := source.intWen 177 sink.bits.fpWen := source.fpWen 178 sink.bits.vecWen := source.vecWen 179 sink.bits.pdest := source.addr 180 } 181 182 // Connect bundles having the same wakeup source 183 issueQueues.zipWithIndex.foreach { case(iq, i) => 184 iq.io.wakeupFromIQ.foreach { wakeUp => 185 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 186 } 187 iq.io.og0Cancel := io.fromDataPath.og0Cancel 188 iq.io.og1Cancel := io.fromDataPath.og1Cancel 189 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 190 } 191 192 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 193 issueQueues.flatMap(_.io.wakeupToIQ) 194 .map(x => (x.bits.exuIdx, x)) 195 .toMap 196 197 // Connect bundles having the same wakeup source 198 io.toSchedulers.wakeupVec.foreach { wakeUp => 199 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 200 } 201 202 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 203 toDp <> issueQueues(i).io.deq 204 } 205 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 206 toDpDy <> issueQueues(i).io.deqDelay 207 } 208 209 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 210 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 211 212 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 213 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 214} 215 216class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 217 extends SchedulerImpBase(wrapper) 218 with HasXSParameter 219{ 220// dontTouch(io.vfWbFuBusyTable) 221 println(s"[SchedulerArithImp] " + 222 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 223 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 224 225 issueQueues.zipWithIndex.foreach { case (iq, i) => 226 iq.io.flush <> io.fromCtrlBlock.flush 227 iq.io.enq <> dispatch2Iq.io.out(i) 228 iq.io.wakeupFromWB := wakeupFromWBVec 229 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 230 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 231 deqResp.bits.respType := RSFeedbackType.issueSuccess 232 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 233 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 234 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 235 236 } 237 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 238 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 239 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 240 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 241 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 242 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 243 244 } 245 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 246 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 247 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 248 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 249 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 250 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 251 252 } 253 254 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 255 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 256 } 257 258 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 259 case imp: IssueQueueIntImp => imp.io.enqJmp 260 case _ => None 261 }.filter(_.nonEmpty).flatMap(_.get) 262 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 263 264 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 265 iqJmp.pc := pc 266 iqJmp.target := target 267 } 268} 269 270class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 271 extends SchedulerImpBase(wrapper) 272 with HasXSParameter 273{ 274 println(s"[SchedulerMemImp] " + 275 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 276 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 277 278 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 279 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 280 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 281 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 282 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 283 284 issueQueues.zipWithIndex.foreach { case (iq, i) => 285 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 286 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 287 deqResp.bits.respType := RSFeedbackType.issueSuccess 288 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 289 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 290 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 291 292 } 293 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 294 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 295 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 296 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 297 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 298 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 299 300 } 301 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 302 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 303 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 304 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 305 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 306 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 307 308 } 309 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 310 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 311 } 312 313 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 314 iq.io.flush <> io.fromCtrlBlock.flush 315 iq.io.enq <> dispatch2Iq.io.out(i) 316 iq.io.wakeupFromWB := wakeupFromWBVec 317 } 318 319 ldAddrIQs.foreach { 320 case imp: IssueQueueMemAddrImp => 321 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 322 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 323 case _ => 324 } 325 326 stAddrIQs.foreach { 327 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 328 case _ => 329 } 330 331 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 332 333 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 334 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 335 val isAllReady = staIQ.ready && stdIQ.ready 336 di.ready := isAllReady 337 staIQ.valid := di.valid && isAllReady 338 stdIQ.valid := di.valid && isAllReady 339 } 340 } 341 342 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 343 s"should be equal to number of data IQs(${stDataIQs})") 344 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 345 stdIQ.io.flush <> io.fromCtrlBlock.flush 346 347 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 348 stdIQEnq.bits := staIQEnq.bits 349 // Store data reuses store addr src(1) in dispatch2iq 350 // [dispatch2iq] --src*------src*(0)--> [staIQ] 351 // \ 352 // ---src*(1)--> [stdIQ] 353 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 354 // instead of dispatch2Iq.io.out(x).bits.src*(1) 355 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 356 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 357 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 358 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 359 } 360 stdIQ.io.wakeupFromWB := wakeupFromWBVec 361 } 362 363 val lsqEnqCtrl = Module(new LsqEnqCtrl) 364 365 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 366 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 367 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 368 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 369 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 370 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 371 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 372} 373