1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.regfile.RfWritePortWithConfig 12import xiangshan.backend.rename.BusyTable 13import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numPregWb(IntData()) 24 val numVfStateWrite = backendParams.numPregWb(VecData()) 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 // params alias 39 private val LoadQueueSize = VirtualLoadQueueSize 40 41 val fromTop = new Bundle { 42 val hartId = Input(UInt(8.W)) 43 } 44 val fromWbFuBusyTable = new Bundle{ 45 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 46 } 47 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 48 49 val fromCtrlBlock = new Bundle { 50 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 51 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 52 val flush = Flipped(ValidIO(new Redirect)) 53 } 54 val fromDispatch = new Bundle { 55 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 56 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 57 } 58 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 59 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 60 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 61 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 62 val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 63 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 64 val fromCancelNetwork = Flipped(MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))) 65 66 val fromSchedulers = new Bundle { 67 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 68 } 69 70 val toSchedulers = new Bundle { 71 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 72 } 73 74 val fromDataPath = new Bundle { 75 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 76 val og0Cancel = Input(ExuVec(backendParams.numExu)) 77 // Todo: remove this after no cancel signal from og1 78 val og1Cancel = Input(ExuVec(backendParams.numExu)) 79 // just be compatible to old code 80 def apply(i: Int)(j: Int) = resp(i)(j) 81 } 82 83 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 84 85 val ldCancel = Vec(backendParams.LduCnt, Flipped(new LoadCancelIO)) 86 87 val memIO = if (params.isMemSchd) Some(new Bundle { 88 val lsqEnqIO = Flipped(new LsqEnqIO) 89 }) else None 90 val fromMem = if (params.isMemSchd) Some(new Bundle { 91 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 92 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 93 val stIssuePtr = Input(new SqPtr()) 94 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 95 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 96 // from lsq 97 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 98 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 99 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 100 }) else None 101 val toMem = if (params.isMemSchd) Some(new Bundle { 102 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 103 }) else None 104} 105 106abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 107 extends LazyModuleImp(wrapper) 108 with HasXSParameter 109{ 110 val io = IO(new SchedulerIO()) 111 112 // alias 113 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 114 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 115 private val schdType = params.schdType 116 117 // Modules 118 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 119 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 120 121 // BusyTable Modules 122 val intBusyTable = schdType match { 123 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs))) 124 case _ => None 125 } 126 127 val vfBusyTable = schdType match { 128 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs))) 129 case _ => None 130 } 131 132 dispatch2Iq.io match { case dp2iq => 133 dp2iq.redirect <> io.fromCtrlBlock.flush 134 dp2iq.in <> io.fromDispatch.uops 135 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 136 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 137 } 138 139 intBusyTable match { 140 case Some(bt) => 141 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 142 btAllocPregs.valid := dpAllocPregs.isInt 143 btAllocPregs.bits := dpAllocPregs.preg 144 } 145 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 146 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 147 wb.bits := io.intWriteBack(i).addr 148 } 149 case None => 150 } 151 152 vfBusyTable match { 153 case Some(bt) => 154 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 155 btAllocPregs.valid := dpAllocPregs.isFp 156 btAllocPregs.bits := dpAllocPregs.preg 157 } 158 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 159 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 160 wb.bits := io.vfWriteBack(i).addr 161 } 162 case None => 163 } 164 165 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 166 val writeback = params.schdType match { 167 case IntScheduler() => io.intWriteBack 168 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 169 case VfScheduler() => io.vfWriteBack 170 case _ => Seq() 171 } 172 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 173 sink.valid := source.wen 174 sink.bits.rfWen := source.intWen 175 sink.bits.fpWen := source.fpWen 176 sink.bits.vecWen := source.vecWen 177 sink.bits.pdest := source.addr 178 } 179 180 // Connect bundles having the same wakeup source 181 issueQueues.zipWithIndex.foreach { case(iq, i) => 182 iq.io.wakeupFromIQ.foreach { wakeUp => 183 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 184 } 185 iq.io.og0Cancel := io.fromDataPath.og0Cancel 186 iq.io.og1Cancel := io.fromDataPath.og1Cancel 187 iq.io.ldCancel := io.ldCancel 188 iq.io.fromCancelNetwork <> io.fromCancelNetwork(i) 189 } 190 191 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 192 issueQueues.flatMap(_.io.wakeupToIQ) 193 .map(x => (x.bits.exuIdx, x)) 194 .toMap 195 196 // Connect bundles having the same wakeup source 197 io.toSchedulers.wakeupVec.foreach { wakeUp => 198 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 199 } 200 201 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 202 toDp <> issueQueues(i).io.deq 203 } 204 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 205 toDpDy <> issueQueues(i).io.deqDelay 206 } 207 208 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 209 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 210 211 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 212 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 213} 214 215class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 216 extends SchedulerImpBase(wrapper) 217 with HasXSParameter 218{ 219// dontTouch(io.vfWbFuBusyTable) 220 println(s"[SchedulerArithImp] " + 221 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 222 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 223 224 issueQueues.zipWithIndex.foreach { case (iq, i) => 225 iq.io.flush <> io.fromCtrlBlock.flush 226 iq.io.enq <> dispatch2Iq.io.out(i) 227 iq.io.wakeupFromWB := wakeupFromWBVec 228 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 229 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 230 deqResp.bits.respType := RSFeedbackType.issueSuccess 231 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 232 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 233 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 234 235 } 236 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 237 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 238 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 239 og0Resp.bits.robIdx := io.fromDataPath(i)(j).og0resp.bits.robIdx 240 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 241 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 242 243 } 244 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 245 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 246 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 247 og1Resp.bits.robIdx := io.fromDataPath(i)(j).og1resp.bits.robIdx 248 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 249 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 250 251 } 252 253 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 254 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 255 } 256 257 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 258 case imp: IssueQueueIntImp => imp.io.enqJmp 259 case _ => None 260 }.filter(_.nonEmpty).flatMap(_.get) 261 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 262 263 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 264 iqJmp.pc := pc 265 iqJmp.target := target 266 } 267} 268 269class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 270 extends SchedulerImpBase(wrapper) 271 with HasXSParameter 272{ 273 println(s"[SchedulerMemImp] " + 274 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 275 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 276 277 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 278 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 279 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 280 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 281 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 282 283 issueQueues.zipWithIndex.foreach { case (iq, i) => 284 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 285 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 286 deqResp.bits.respType := RSFeedbackType.issueSuccess 287 deqResp.bits.robIdx := iq.io.deq(j).bits.common.robIdx 288 deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B) 289 deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType 290 291 } 292 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 293 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 294 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 295 og0Resp.bits.robIdx := io.fromDataPath(i)(j).og0resp.bits.robIdx 296 og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen 297 og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType 298 299 } 300 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 301 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 302 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 303 og1Resp.bits.robIdx := io.fromDataPath(i)(j).og1resp.bits.robIdx 304 og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen 305 og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType 306 307 } 308 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 309 finalIssueResp := io.loadFinalIssueResp(i)(j) 310 }) 311 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 312 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 313 } 314 315 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 316 iq.io.flush <> io.fromCtrlBlock.flush 317 iq.io.enq <> dispatch2Iq.io.out(i) 318 iq.io.wakeupFromWB := wakeupFromWBVec 319 } 320 321 ldAddrIQs.foreach { 322 case imp: IssueQueueMemAddrImp => 323 imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 324 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 325 case _ => 326 } 327 328 stAddrIQs.foreach { 329 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 330 case _ => 331 } 332 333 private val staIdxSeq = issueQueues.filter(iq => iq.params.StaCnt > 0).map(iq => iq.params.idxInSchBlk) 334 335 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 336 dispatch2Iq.io.out(idxInSchBlk).zip(stAddrIQs(i).io.enq).zip(stDataIQs(i).io.enq).foreach{ case((di, staIQ), stdIQ) => 337 val isAllReady = staIQ.ready && stdIQ.ready 338 di.ready := isAllReady 339 staIQ.valid := di.valid && isAllReady 340 stdIQ.valid := di.valid && isAllReady 341 } 342 } 343 344 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 345 s"should be equal to number of data IQs(${stDataIQs})") 346 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 347 stdIQ.io.flush <> io.fromCtrlBlock.flush 348 349 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 350 stdIQEnq.bits := staIQEnq.bits 351 // Store data reuses store addr src(1) in dispatch2iq 352 // [dispatch2iq] --src*------src*(0)--> [staIQ] 353 // \ 354 // ---src*(1)--> [stdIQ] 355 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 356 // instead of dispatch2Iq.io.out(x).bits.src*(1) 357 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 358 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 359 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 360 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 361 } 362 stdIQ.io.wakeupFromWB := wakeupFromWBVec 363 } 364 365 val lsqEnqCtrl = Module(new LsqEnqCtrl) 366 367 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 368 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 369 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 370 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 371 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 372 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 373 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 374} 375