xref: /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala (revision bf35baadc696c036c1c015fd05dc490255f3e71f) 
1package xiangshan.backend.issue
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3.util._
5import utils.SeqUtils
6import xiangshan.backend.Bundles.{ExuInput, ExuOutput, IssueQueueWakeUpBundle}
7import xiangshan.backend.datapath.WakeUpSource
8import xiangshan.backend.datapath.WbConfig.WbConfig
9
10case class SchdBlockParams(
11  issueBlockParams: Seq[IssueBlockParams],
12  numPregs        : Int,
13  numRfReadWrite  : Option[(Int, Int)],
14  numDeqOutside   : Int,
15  schdType        : SchedulerType,
16  rfDataWidth     : Int,
17  numUopIn        : Int,
18) {
19  def isMemSchd: Boolean = schdType == MemScheduler()
20
21  def isIntSchd: Boolean = schdType == IntScheduler()
22
23  def isVfSchd: Boolean = schdType == VfScheduler()
24
25  def JmpCnt: Int = issueBlockParams.map(_.JmpCnt).sum
26
27  def BrhCnt: Int = issueBlockParams.map(_.BrhCnt).sum
28
29  def I2fCnt: Int = issueBlockParams.map(_.I2fCnt).sum
30
31  def CsrCnt: Int = issueBlockParams.map(_.CsrCnt).sum
32
33  def AluCnt: Int = issueBlockParams.map(_.AluCnt).sum
34
35  def MulCnt: Int = issueBlockParams.map(_.MulCnt).sum
36
37  def DivCnt: Int = issueBlockParams.map(_.DivCnt).sum
38
39  def FenceCnt: Int = issueBlockParams.map(_.FenceCnt).sum
40
41  def BkuCnt: Int = issueBlockParams.map(_.BkuCnt).sum
42
43  def VsetCnt: Int = issueBlockParams.map(_.VsetCnt).sum
44
45  def FmacCnt: Int = issueBlockParams.map(_.FmacCnt).sum
46
47  def FmiscCnt: Int = issueBlockParams.map(_.FmiscCnt).sum
48
49  def FDivSqrtCnt: Int = issueBlockParams.map(_.fDivSqrtCnt).sum
50
51  def LduCnt: Int = issueBlockParams.map(_.LduCnt).sum
52
53  def StaCnt: Int = issueBlockParams.map(_.StaCnt).sum
54
55  def StdCnt: Int = issueBlockParams.map(_.StdCnt).sum
56
57  def MouCnt: Int = issueBlockParams.map(_.MouCnt).sum
58
59  def VipuCnt: Int = issueBlockParams.map(_.VipuCnt).sum
60
61  def VfpuCnt: Int = issueBlockParams.map(_.VfpuCnt).sum
62
63  def VlduCnt: Int = issueBlockParams.map(_.VlduCnt).sum
64
65  def VstuCnt: Int = issueBlockParams.map(_.VstuCnt).sum
66
67  def numExu: Int = issueBlockParams.map(_.exuBlockParams.count(!_.hasStdFu)).sum
68
69  def hasCSR = CsrCnt > 0
70
71  def hasFence = FenceCnt > 0
72
73  def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum
74
75  def numWriteFpRf: Int = issueBlockParams.map(_.numWriteFpRf).sum
76
77  def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum
78
79  def numWriteVfRf: Int = issueBlockParams.map(_.numWriteVfRf).sum
80
81  def numNoDataWB: Int = issueBlockParams.map(_.numNoDataWB).sum
82
83  def numPcReadPort = {
84    val bjIssueQueues = issueBlockParams.filter(x => (x.JmpCnt + x.BrhCnt + x.FenceCnt) > 0)
85    if (bjIssueQueues.map(x => x.numEnq).sum > 0) numUopIn else 0
86  }
87
88  def needSrcFrm: Boolean = issueBlockParams.map(_.needSrcFrm).reduce(_ || _)
89
90  def numRedirect: Int = issueBlockParams.map(_.numRedirect).sum
91
92  def pregIdxWidth: Int = log2Up(numPregs)
93
94  def numWakeupFromWB: Int = schdType match {
95    case IntScheduler() | VfScheduler() => 8
96    case MemScheduler() => 16 // Todo
97    case _ => 0
98  }
99
100  def numIntRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numIntSrc).sum).sum
101
102  def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(x => x.numFpSrc + x.numVecSrc).sum).sum
103
104  // Todo: 14R8W
105  def numIntRfRead: Int = numIntRfReadByExu
106
107  def genExuInputBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = {
108    MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledBundle))
109  }
110
111  def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = {
112    MixedVec(this.issueBlockParams.map(_.genExuOutputDecoupledBundle))
113  }
114
115  def genExuOutputValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuOutput]]] = {
116    MixedVec(this.issueBlockParams.map(_.genExuOutputValidBundle))
117  }
118
119  def wakeUpInExuSources: Seq[WakeUpSource] = {
120    SeqUtils.distinctBy(
121      issueBlockParams
122        .flatMap(_.wakeUpInExuSources)
123    )(_.name)
124  }
125
126  def wakeUpOutExuSources: Seq[WakeUpSource] = {
127    SeqUtils.distinctBy(
128      issueBlockParams
129        .flatMap(_.wakeUpOutExuSources)
130    )(_.name)
131  }
132
133  def genWakeUpInValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWakeUpBundle]] = {
134    MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueWakeUpBundle(x.name))))
135  }
136
137  def genWakeUpOutValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWakeUpBundle]] = {
138    MixedVec(this.wakeUpOutExuSources.map(x => ValidIO(new IssueQueueWakeUpBundle(x.name))))
139  }
140
141  // cfgs(issueIdx)(exuIdx)(set of exu's wb)
142  def getWbCfgs: Seq[Seq[Set[WbConfig]]] = {
143    this.issueBlockParams.map(_.getWbCfgs)
144  }
145}
146