xref: /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala (revision b133b458c6613564f0a6a4fe81d1262db387530a) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3.util._
5import utils.SeqUtils
6import xiangshan.backend.BackendParams
7import xiangshan.backend.Bundles._
8import xiangshan.backend.datapath.WakeUpSource
9import xiangshan.backend.datapath.WbConfig.PregWB
10
11case class SchdBlockParams(
12  issueBlockParams: Seq[IssueBlockParams],
13  numPregs        : Int,
14  numDeqOutside   : Int,
15  schdType        : SchedulerType,
16  rfDataWidth     : Int,
17  numUopIn        : Int,
18) {
19  var backendParam: BackendParams = null
20
21  def isMemSchd: Boolean = schdType == MemScheduler()
22
23  def isIntSchd: Boolean = schdType == IntScheduler()
24
25  def isVfSchd: Boolean = schdType == VfScheduler()
26
27  def JmpCnt: Int = issueBlockParams.map(_.JmpCnt).sum
28
29  def BrhCnt: Int = issueBlockParams.map(_.BrhCnt).sum
30
31  def I2fCnt: Int = issueBlockParams.map(_.I2fCnt).sum
32
33  def CsrCnt: Int = issueBlockParams.map(_.CsrCnt).sum
34
35  def AluCnt: Int = issueBlockParams.map(_.AluCnt).sum
36
37  def MulCnt: Int = issueBlockParams.map(_.MulCnt).sum
38
39  def DivCnt: Int = issueBlockParams.map(_.DivCnt).sum
40
41  def FenceCnt: Int = issueBlockParams.map(_.FenceCnt).sum
42
43  def BkuCnt: Int = issueBlockParams.map(_.BkuCnt).sum
44
45  def VsetCnt: Int = issueBlockParams.map(_.VsetCnt).sum
46
47  def FmacCnt: Int = issueBlockParams.map(_.FmacCnt).sum
48
49  def FmiscCnt: Int = issueBlockParams.map(_.FmiscCnt).sum
50
51  def FDivSqrtCnt: Int = issueBlockParams.map(_.fDivSqrtCnt).sum
52
53  def LduCnt: Int = issueBlockParams.map(_.LduCnt).sum
54
55  def StaCnt: Int = issueBlockParams.map(_.StaCnt).sum
56
57  def StdCnt: Int = issueBlockParams.map(_.StdCnt).sum
58
59  def MouCnt: Int = issueBlockParams.map(_.MouCnt).sum
60
61  def HyuCnt: Int = issueBlockParams.map(_.HyuCnt).sum
62
63  def VipuCnt: Int = issueBlockParams.map(_.VipuCnt).sum
64
65  def VfpuCnt: Int = issueBlockParams.map(_.VfpuCnt).sum
66
67  def VlduCnt: Int = issueBlockParams.map(_.VlduCnt).sum
68
69  def VstuCnt: Int = issueBlockParams.map(_.VstuCnt).sum
70
71  def numExu: Int = issueBlockParams.map(_.exuBlockParams.size).sum
72
73  def hasCSR = CsrCnt > 0
74
75  def hasFence = FenceCnt > 0
76
77  def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum
78
79  def numWriteFpRf: Int = issueBlockParams.map(_.numWriteFpRf).sum
80
81  def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum
82
83  def numWriteVfRf: Int = issueBlockParams.map(_.numWriteVfRf).sum
84
85  def numNoDataWB: Int = issueBlockParams.map(_.numNoDataWB).sum
86
87  def numPcReadPort = {
88    val bjIssueQueues = issueBlockParams.filter(x => (x.JmpCnt + x.BrhCnt + x.FenceCnt) > 0)
89    if (bjIssueQueues.map(x => x.numEnq).sum > 0) numUopIn else 0
90  }
91
92  def needSrcFrm: Boolean = issueBlockParams.map(_.needSrcFrm).reduce(_ || _)
93
94  def numRedirect: Int = issueBlockParams.map(_.numRedirect).sum
95
96  def pregIdxWidth: Int = log2Up(numPregs)
97
98  def numWakeupFromWB: Int = schdType match {
99    case IntScheduler() | VfScheduler() => 8
100    case MemScheduler() => 16 // Todo
101    case _ => 0
102  }
103
104  def numIntRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numIntSrc).sum).sum
105
106  def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(x => x.numFpSrc + x.numVecSrc).sum).sum
107
108  def bindBackendParam(param: BackendParams): Unit = {
109    backendParam = param
110  }
111
112  def genExuInputBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = {
113    MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledBundle))
114  }
115
116  def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = {
117    MixedVec(this.issueBlockParams.map(_.genExuOutputDecoupledBundle))
118  }
119
120  def genExuOutputValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuOutput]]] = {
121    MixedVec(this.issueBlockParams.map(_.genExuOutputValidBundle))
122  }
123
124  def genExuBypassValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuBypassBundle]]] = {
125    MixedVec(this.issueBlockParams.map(_.genExuBypassValidBundle))
126  }
127
128  def wakeUpInExuSources: Seq[WakeUpSource] = {
129    SeqUtils.distinctBy(
130      issueBlockParams
131        .flatMap(_.wakeUpInExuSources)
132    )(_.name)
133  }
134
135  def wakeUpOutExuSources: Seq[WakeUpSource] = {
136    SeqUtils.distinctBy(
137      issueBlockParams
138        .flatMap(_.wakeUpOutExuSources)
139    )(_.name)
140  }
141
142  def genIQWakeUpInValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = {
143    MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam))))
144  }
145
146  def genIQWakeUpOutValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = {
147    MixedVec(this.wakeUpOutExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam))))
148  }
149
150  def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = {
151    val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match {
152      case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq
153      case _ => Seq()
154    }
155    val vfBundle = schdType match {
156      case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq
157      case _ => Seq()
158    }
159    MixedVec(intBundle ++ vfBundle)
160  }
161
162  // cfgs(issueIdx)(exuIdx)(set of exu's wb)
163  def getWbCfgs: Seq[Seq[Set[PregWB]]] = {
164    this.issueBlockParams.map(_.getWbCfgs)
165  }
166}
167