1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3.util._ 5import utils.SeqUtils 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles._ 8import xiangshan.backend.datapath.WakeUpSource 9import xiangshan.backend.datapath.WbConfig.PregWB 10 11case class SchdBlockParams( 12 issueBlockParams: Seq[IssueBlockParams], 13 numPregs : Int, 14 numDeqOutside : Int, 15 schdType : SchedulerType, 16 rfDataWidth : Int, 17 numUopIn : Int, 18) { 19 var backendParam: BackendParams = null 20 21 def isMemSchd: Boolean = schdType == MemScheduler() 22 23 def isIntSchd: Boolean = schdType == IntScheduler() 24 25 def isFpSchd: Boolean = schdType == FpScheduler() 26 27 def isVfSchd: Boolean = schdType == VfScheduler() 28 29 def JmpCnt: Int = issueBlockParams.map(_.JmpCnt).sum 30 31 def BrhCnt: Int = issueBlockParams.map(_.BrhCnt).sum 32 33 def I2fCnt: Int = issueBlockParams.map(_.I2fCnt).sum 34 35 def CsrCnt: Int = issueBlockParams.map(_.CsrCnt).sum 36 37 def AluCnt: Int = issueBlockParams.map(_.AluCnt).sum 38 39 def MulCnt: Int = issueBlockParams.map(_.MulCnt).sum 40 41 def DivCnt: Int = issueBlockParams.map(_.DivCnt).sum 42 43 def FenceCnt: Int = issueBlockParams.map(_.FenceCnt).sum 44 45 def BkuCnt: Int = issueBlockParams.map(_.BkuCnt).sum 46 47 def VsetCnt: Int = issueBlockParams.map(_.VsetCnt).sum 48 49 def FmacCnt: Int = issueBlockParams.map(_.FmacCnt).sum 50 51 def FDivSqrtCnt: Int = issueBlockParams.map(_.fDivSqrtCnt).sum 52 53 def LduCnt: Int = issueBlockParams.map(_.LduCnt).sum 54 55 def StaCnt: Int = issueBlockParams.map(_.StaCnt).sum 56 57 def StdCnt: Int = issueBlockParams.map(_.StdCnt).sum 58 59 def MouCnt: Int = issueBlockParams.map(_.MouCnt).sum 60 61 def HyuCnt: Int = issueBlockParams.map(_.HyuCnt).sum 62 63 def LdExuCnt: Int = issueBlockParams.map(_.LdExuCnt).sum 64 65 def VipuCnt: Int = issueBlockParams.map(_.VipuCnt).sum 66 67 def VfpuCnt: Int = issueBlockParams.map(_.VfpuCnt).sum 68 69 def VlduCnt: Int = issueBlockParams.map(_.VlduCnt).sum 70 71 def VstuCnt: Int = issueBlockParams.map(_.VstuCnt).sum 72 73 def numExu: Int = issueBlockParams.map(_.exuBlockParams.count(!_.fakeUnit)).sum 74 75 def hasCSR = CsrCnt > 0 76 77 def hasFence = FenceCnt > 0 78 79 def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum 80 81 def numWriteFpRf: Int = issueBlockParams.map(_.numWriteFpRf).sum 82 83 def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum 84 85 def numWriteVfRf: Int = issueBlockParams.map(_.numWriteVfRf).sum 86 87 def numNoDataWB: Int = issueBlockParams.map(_.numNoDataWB).sum 88 89 def numPcReadPort = { 90 val bjIssueQueues = issueBlockParams.filter(x => (x.JmpCnt + x.BrhCnt + x.FenceCnt) > 0) 91 if (bjIssueQueues.map(x => x.numEnq).sum > 0) numUopIn else 0 92 } 93 94 def needSrcFrm: Boolean = issueBlockParams.map(_.needSrcFrm).reduce(_ || _) 95 96 def needSrcVxrm: Boolean = issueBlockParams.map(_.needSrcVxrm).reduce(_ || _) 97 98 def writeVConfig: Boolean = issueBlockParams.map(_.writeVConfig).reduce(_ || _) 99 100 def writeVType: Boolean = issueBlockParams.map(_.writeVType).reduce(_ || _) 101 102 def numRedirect: Int = issueBlockParams.map(_.numRedirect).sum 103 104 def pregIdxWidth: Int = log2Up(numPregs) 105 106 def numWakeupFromWB: Int = schdType match { 107 case IntScheduler() | VfScheduler() => 8 108 case MemScheduler() => 16 // Todo 109 case _ => 0 110 } 111 112 def numIntRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numIntSrc).sum).sum 113 114 def numFpRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numFpSrc).sum).sum 115 116 def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(x => x.numFpSrc + x.numVecSrc).sum).sum 117 118 def bindBackendParam(param: BackendParams): Unit = { 119 backendParam = param 120 } 121 122 def genExuInputBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = { 123 MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledBundle)) 124 } 125 126 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = { 127 MixedVec(this.issueBlockParams.map(_.genExuOutputDecoupledBundle)) 128 } 129 130 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuOutput]]] = { 131 MixedVec(this.issueBlockParams.map(_.genExuOutputValidBundle)) 132 } 133 134 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuBypassBundle]]] = { 135 MixedVec(this.issueBlockParams.map(_.genExuBypassValidBundle)) 136 } 137 138 def wakeUpInExuSources: Seq[WakeUpSource] = { 139 SeqUtils.distinctBy( 140 issueBlockParams 141 .flatMap(_.wakeUpInExuSources) 142 )(_.name) 143 } 144 145 def wakeUpOutExuSources: Seq[WakeUpSource] = { 146 SeqUtils.distinctBy( 147 issueBlockParams 148 .flatMap(_.wakeUpOutExuSources) 149 )(_.name) 150 } 151 152 def genIQWakeUpInValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 153 MixedVec(this.wakeUpInExuSources.map(x => { 154 val param = x.getExuParam(backendParam.allExuParams) 155 val isCopyPdest = param.copyWakeupOut 156 val copyNum = param.copyNum 157 ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam, isCopyPdest, copyNum)) 158 }) 159 ) 160 } 161 162 def genIQWakeUpOutValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 163 MixedVec(this.wakeUpOutExuSources.map(x => { 164 val param = x.getExuParam(backendParam.allExuParams) 165 val isCopyPdest = param.copyWakeupOut 166 val copyNum = param.copyNum 167 ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam, isCopyPdest, copyNum)) 168 }) 169 ) 170 } 171 172 def genWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 173 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 174 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 175 case _ => Seq() 176 } 177 val fpBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 178 case FpScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 179 case _ => Seq() 180 } 181 val vfBundle = schdType match { 182 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 183 case _ => Seq() 184 } 185 MixedVec(intBundle ++ fpBundle ++ vfBundle) 186 } 187 188 def genIntWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 189 MixedVec(backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 190 } 191 192 def genFpWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 193 MixedVec(backendParam.getFpWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 194 } 195 196 def genVfWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 197 MixedVec(backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 198 } 199 200 // cfgs(issueIdx)(exuIdx)(set of exu's wb) 201 def getWbCfgs: Seq[Seq[Set[PregWB]]] = { 202 this.issueBlockParams.map(_.getWbCfgs) 203 } 204} 205