1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3.util._ 5import utils.SeqUtils 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles._ 8import xiangshan.backend.datapath.WakeUpSource 9import xiangshan.backend.datapath.WbConfig.PregWB 10 11case class SchdBlockParams( 12 issueBlockParams: Seq[IssueBlockParams], 13 numPregs : Int, 14 numDeqOutside : Int, 15 schdType : SchedulerType, 16 rfDataWidth : Int, 17 numUopIn : Int, 18) { 19 var backendParam: BackendParams = null 20 21 def isMemSchd: Boolean = schdType == MemScheduler() 22 23 def isIntSchd: Boolean = schdType == IntScheduler() 24 25 def isVfSchd: Boolean = schdType == VfScheduler() 26 27 def JmpCnt: Int = issueBlockParams.map(_.JmpCnt).sum 28 29 def BrhCnt: Int = issueBlockParams.map(_.BrhCnt).sum 30 31 def I2fCnt: Int = issueBlockParams.map(_.I2fCnt).sum 32 33 def CsrCnt: Int = issueBlockParams.map(_.CsrCnt).sum 34 35 def AluCnt: Int = issueBlockParams.map(_.AluCnt).sum 36 37 def MulCnt: Int = issueBlockParams.map(_.MulCnt).sum 38 39 def DivCnt: Int = issueBlockParams.map(_.DivCnt).sum 40 41 def FenceCnt: Int = issueBlockParams.map(_.FenceCnt).sum 42 43 def BkuCnt: Int = issueBlockParams.map(_.BkuCnt).sum 44 45 def VsetCnt: Int = issueBlockParams.map(_.VsetCnt).sum 46 47 def FmacCnt: Int = issueBlockParams.map(_.FmacCnt).sum 48 49 def FmiscCnt: Int = issueBlockParams.map(_.FmiscCnt).sum 50 51 def FDivSqrtCnt: Int = issueBlockParams.map(_.fDivSqrtCnt).sum 52 53 def LduCnt: Int = issueBlockParams.map(_.LduCnt).sum 54 55 def StaCnt: Int = issueBlockParams.map(_.StaCnt).sum 56 57 def StdCnt: Int = issueBlockParams.map(_.StdCnt).sum 58 59 def MouCnt: Int = issueBlockParams.map(_.MouCnt).sum 60 61 def HyuCnt: Int = issueBlockParams.map(_.HyuCnt).sum 62 63 def LdExuCnt: Int = issueBlockParams.map(_.LdExuCnt).sum 64 65 def VipuCnt: Int = issueBlockParams.map(_.VipuCnt).sum 66 67 def VfpuCnt: Int = issueBlockParams.map(_.VfpuCnt).sum 68 69 def VlduCnt: Int = issueBlockParams.map(_.VlduCnt).sum 70 71 def VstuCnt: Int = issueBlockParams.map(_.VstuCnt).sum 72 73 def numExu: Int = issueBlockParams.map(_.exuBlockParams.count(!_.fakeUnit)).sum 74 75 def hasCSR = CsrCnt > 0 76 77 def hasFence = FenceCnt > 0 78 79 def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum 80 81 def numWriteFpRf: Int = issueBlockParams.map(_.numWriteFpRf).sum 82 83 def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum 84 85 def numWriteVfRf: Int = issueBlockParams.map(_.numWriteVfRf).sum 86 87 def numNoDataWB: Int = issueBlockParams.map(_.numNoDataWB).sum 88 89 def numPcReadPort = { 90 val bjIssueQueues = issueBlockParams.filter(x => (x.JmpCnt + x.BrhCnt + x.FenceCnt) > 0) 91 if (bjIssueQueues.map(x => x.numEnq).sum > 0) numUopIn else 0 92 } 93 94 def needSrcFrm: Boolean = issueBlockParams.map(_.needSrcFrm).reduce(_ || _) 95 96 def needSrcVxrm: Boolean = issueBlockParams.map(_.needSrcVxrm).reduce(_ || _) 97 98 def writeVType: Boolean = issueBlockParams.map(_.writeVType).reduce(_ || _) 99 100 def numRedirect: Int = issueBlockParams.map(_.numRedirect).sum 101 102 def pregIdxWidth: Int = log2Up(numPregs) 103 104 def numWakeupFromWB: Int = schdType match { 105 case IntScheduler() | VfScheduler() => 8 106 case MemScheduler() => 16 // Todo 107 case _ => 0 108 } 109 110 def numIntRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numIntSrc).sum).sum 111 112 def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(x => x.numFpSrc + x.numVecSrc).sum).sum 113 114 def bindBackendParam(param: BackendParams): Unit = { 115 backendParam = param 116 } 117 118 def genExuInputBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = { 119 MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledBundle)) 120 } 121 122 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = { 123 MixedVec(this.issueBlockParams.map(_.genExuOutputDecoupledBundle)) 124 } 125 126 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuOutput]]] = { 127 MixedVec(this.issueBlockParams.map(_.genExuOutputValidBundle)) 128 } 129 130 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuBypassBundle]]] = { 131 MixedVec(this.issueBlockParams.map(_.genExuBypassValidBundle)) 132 } 133 134 def wakeUpInExuSources: Seq[WakeUpSource] = { 135 SeqUtils.distinctBy( 136 issueBlockParams 137 .flatMap(_.wakeUpInExuSources) 138 )(_.name) 139 } 140 141 def wakeUpOutExuSources: Seq[WakeUpSource] = { 142 SeqUtils.distinctBy( 143 issueBlockParams 144 .flatMap(_.wakeUpOutExuSources) 145 )(_.name) 146 } 147 148 def genIQWakeUpInValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 149 MixedVec(this.wakeUpInExuSources.map(x => { 150 val param = x.getExuParam(backendParam.allExuParams) 151 val isCopyPdest = param.copyWakeupOut 152 val copyNum = param.copyNum 153 ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam, isCopyPdest, copyNum)) 154 }) 155 ) 156 } 157 158 def genIQWakeUpOutValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 159 MixedVec(this.wakeUpOutExuSources.map(x => { 160 val param = x.getExuParam(backendParam.allExuParams) 161 val isCopyPdest = param.copyWakeupOut 162 val copyNum = param.copyNum 163 ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam, isCopyPdest, copyNum)) 164 }) 165 ) 166 } 167 168 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 169 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 170 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 171 case _ => Seq() 172 } 173 val vfBundle = schdType match { 174 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 175 case _ => Seq() 176 } 177 MixedVec(intBundle ++ vfBundle) 178 } 179 180 def genIntWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 181 MixedVec(backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 182 } 183 184 def genVfWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 185 MixedVec(backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 186 } 187 188 // cfgs(issueIdx)(exuIdx)(set of exu's wb) 189 def getWbCfgs: Seq[Seq[Set[PregWB]]] = { 190 this.issueBlockParams.map(_.getWbCfgs) 191 } 192} 193