1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3.util._ 5import utils.SeqUtils 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles._ 8import xiangshan.backend.datapath.WakeUpSource 9import xiangshan.backend.datapath.WbConfig.PregWB 10 11case class SchdBlockParams( 12 issueBlockParams: Seq[IssueBlockParams], 13 numPregs : Int, 14 numDeqOutside : Int, 15 schdType : SchedulerType, 16 rfDataWidth : Int, 17 numUopIn : Int, 18) { 19 var backendParam: BackendParams = null 20 21 def isMemSchd: Boolean = schdType == MemScheduler() 22 23 def isIntSchd: Boolean = schdType == IntScheduler() 24 25 def isFpSchd: Boolean = schdType == FpScheduler() 26 27 def isVfSchd: Boolean = schdType == VfScheduler() 28 29 def JmpCnt: Int = issueBlockParams.map(_.JmpCnt).sum 30 31 def BrhCnt: Int = issueBlockParams.map(_.BrhCnt).sum 32 33 def I2fCnt: Int = issueBlockParams.map(_.I2fCnt).sum 34 35 def CsrCnt: Int = issueBlockParams.map(_.CsrCnt).sum 36 37 def AluCnt: Int = issueBlockParams.map(_.AluCnt).sum 38 39 def MulCnt: Int = issueBlockParams.map(_.MulCnt).sum 40 41 def DivCnt: Int = issueBlockParams.map(_.DivCnt).sum 42 43 def FenceCnt: Int = issueBlockParams.map(_.FenceCnt).sum 44 45 def BkuCnt: Int = issueBlockParams.map(_.BkuCnt).sum 46 47 def VsetCnt: Int = issueBlockParams.map(_.VsetCnt).sum 48 49 def FmacCnt: Int = issueBlockParams.map(_.FmacCnt).sum 50 51 def FDivSqrtCnt: Int = issueBlockParams.map(_.fDivSqrtCnt).sum 52 53 def LduCnt: Int = issueBlockParams.map(_.LduCnt).sum 54 55 def StaCnt: Int = issueBlockParams.map(_.StaCnt).sum 56 57 def StdCnt: Int = issueBlockParams.map(_.StdCnt).sum 58 59 def MouCnt: Int = issueBlockParams.map(_.MouCnt).sum 60 61 def HyuCnt: Int = issueBlockParams.map(_.HyuCnt).sum 62 63 def LdExuCnt: Int = issueBlockParams.map(_.LdExuCnt).sum 64 65 def VipuCnt: Int = issueBlockParams.map(_.VipuCnt).sum 66 67 def VfpuCnt: Int = issueBlockParams.map(_.VfpuCnt).sum 68 69 def VlduCnt: Int = issueBlockParams.map(_.VlduCnt).sum 70 71 def VstuCnt: Int = issueBlockParams.map(_.VstuCnt).sum 72 73 def numExu: Int = issueBlockParams.map(_.exuBlockParams.count(!_.fakeUnit)).sum 74 75 def hasCSR = CsrCnt > 0 76 77 def hasFence = FenceCnt > 0 78 79 def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum 80 81 def numWriteFpRf: Int = issueBlockParams.map(_.numWriteFpRf).sum 82 83 def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum 84 85 def numWriteVfRf: Int = issueBlockParams.map(_.numWriteVfRf).sum 86 87 def numNoDataWB: Int = issueBlockParams.map(_.numNoDataWB).sum 88 89 def numPcReadPort = { 90 val bjIssueQueues = issueBlockParams.filter(x => (x.JmpCnt + x.BrhCnt + x.FenceCnt) > 0) 91 if (bjIssueQueues.map(x => x.numEnq).sum > 0) numUopIn else 0 92 } 93 94 def needOg2Resp: Boolean = isVfSchd || isMemSchd && issueBlockParams.map(_.needOg2Resp).reduce(_ || _) 95 96 def needSrcFrm: Boolean = issueBlockParams.map(_.needSrcFrm).reduce(_ || _) 97 98 def needSrcVxrm: Boolean = issueBlockParams.map(_.needSrcVxrm).reduce(_ || _) 99 100 def writeVConfig: Boolean = issueBlockParams.map(_.writeVConfig).reduce(_ || _) 101 102 def writeVType: Boolean = issueBlockParams.map(_.writeVType).reduce(_ || _) 103 104 def numRedirect: Int = issueBlockParams.map(_.numRedirect).sum 105 106 def pregIdxWidth: Int = log2Up(numPregs) 107 108 def numWakeupFromWB: Int = schdType match { 109 case IntScheduler() | VfScheduler() => 8 110 case MemScheduler() => 16 // Todo 111 case _ => 0 112 } 113 114 def numIntRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numIntSrc).sum).sum 115 116 def numFpRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numFpSrc).sum).sum 117 118 def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numVecSrc).sum).sum 119 120 def numV0RfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numV0Src).sum).sum 121 122 def numVlRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numVlSrc).sum).sum 123 124 def bindBackendParam(param: BackendParams): Unit = { 125 backendParam = param 126 } 127 128 def numWriteRegCache: Int = issueBlockParams.map(_.numWriteRegCache).sum 129 130 def needWriteRegCache: Boolean = numWriteRegCache > 0 131 132 def genExuInputBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = { 133 MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledBundle)) 134 } 135 136 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = { 137 MixedVec(this.issueBlockParams.map(_.genExuOutputDecoupledBundle)) 138 } 139 140 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuOutput]]] = { 141 MixedVec(this.issueBlockParams.map(_.genExuOutputValidBundle)) 142 } 143 144 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuBypassBundle]]] = { 145 MixedVec(this.issueBlockParams.map(_.genExuBypassValidBundle)) 146 } 147 148 def wakeUpInExuSources: Seq[WakeUpSource] = { 149 SeqUtils.distinctBy( 150 issueBlockParams 151 .flatMap(_.wakeUpInExuSources) 152 )(_.name) 153 } 154 155 def wakeUpOutExuSources: Seq[WakeUpSource] = { 156 SeqUtils.distinctBy( 157 issueBlockParams 158 .flatMap(_.wakeUpOutExuSources) 159 )(_.name) 160 } 161 162 def genIQWakeUpInValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 163 MixedVec(this.wakeUpInExuSources.map(x => { 164 val param = x.getExuParam(backendParam.allExuParams) 165 val isCopyPdest = param.copyWakeupOut 166 val copyNum = param.copyNum 167 ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam, isCopyPdest, copyNum)) 168 }) 169 ) 170 } 171 172 def genIQWakeUpOutValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 173 MixedVec(this.wakeUpOutExuSources.map(x => { 174 val param = x.getExuParam(backendParam.allExuParams) 175 val isCopyPdest = param.copyWakeupOut 176 val copyNum = param.copyNum 177 ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam, isCopyPdest, copyNum)) 178 }) 179 ) 180 } 181 182 def genWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 183 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 184 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 185 case _ => Seq() 186 } 187 val fpBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 188 case FpScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 189 case _ => Seq() 190 } 191 val vfBundle = schdType match { 192 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 193 case _ => Seq() 194 } 195 val v0Bundle = schdType match { 196 case VfScheduler() | MemScheduler() => backendParam.getV0WBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 197 case _ => Seq() 198 } 199 val vlBundle = schdType match { 200 case VfScheduler() | MemScheduler() => backendParam.getVlWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 201 case _ => Seq() 202 } 203 MixedVec(intBundle ++ fpBundle ++ vfBundle ++ v0Bundle ++ vlBundle) 204 } 205 206 def genIntWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 207 MixedVec(backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 208 } 209 210 def genFpWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 211 MixedVec(backendParam.getFpWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 212 } 213 214 def genVfWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 215 MixedVec(backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 216 } 217 218 def genV0WBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 219 MixedVec(backendParam.getV0WBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 220 } 221 222 def genVlWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 223 MixedVec(backendParam.getVlWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 224 } 225 226 // cfgs(issueIdx)(exuIdx)(set of exu's wb) 227 def getWbCfgs: Seq[Seq[Set[PregWB]]] = { 228 this.issueBlockParams.map(_.getWbCfgs) 229 } 230} 231