xref: /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala (revision 10fe9778fa9a2bab57fff10c0822c5ac2973ba8f) 
1package xiangshan.backend.issue
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3.util._
5import utils.SeqUtils
6import xiangshan.backend.BackendParams
7import xiangshan.backend.Bundles._
8import xiangshan.backend.datapath.WakeUpSource
9import xiangshan.backend.datapath.WbConfig.WbConfig
10
11case class SchdBlockParams(
12  issueBlockParams: Seq[IssueBlockParams],
13  numPregs        : Int,
14  numRfReadWrite  : Option[(Int, Int)],
15  numDeqOutside   : Int,
16  schdType        : SchedulerType,
17  rfDataWidth     : Int,
18  numUopIn        : Int,
19) {
20  var backendParam: BackendParams = null
21
22  def isMemSchd: Boolean = schdType == MemScheduler()
23
24  def isIntSchd: Boolean = schdType == IntScheduler()
25
26  def isVfSchd: Boolean = schdType == VfScheduler()
27
28  def JmpCnt: Int = issueBlockParams.map(_.JmpCnt).sum
29
30  def BrhCnt: Int = issueBlockParams.map(_.BrhCnt).sum
31
32  def I2fCnt: Int = issueBlockParams.map(_.I2fCnt).sum
33
34  def CsrCnt: Int = issueBlockParams.map(_.CsrCnt).sum
35
36  def AluCnt: Int = issueBlockParams.map(_.AluCnt).sum
37
38  def MulCnt: Int = issueBlockParams.map(_.MulCnt).sum
39
40  def DivCnt: Int = issueBlockParams.map(_.DivCnt).sum
41
42  def FenceCnt: Int = issueBlockParams.map(_.FenceCnt).sum
43
44  def BkuCnt: Int = issueBlockParams.map(_.BkuCnt).sum
45
46  def VsetCnt: Int = issueBlockParams.map(_.VsetCnt).sum
47
48  def FmacCnt: Int = issueBlockParams.map(_.FmacCnt).sum
49
50  def FmiscCnt: Int = issueBlockParams.map(_.FmiscCnt).sum
51
52  def FDivSqrtCnt: Int = issueBlockParams.map(_.fDivSqrtCnt).sum
53
54  def LduCnt: Int = issueBlockParams.map(_.LduCnt).sum
55
56  def StaCnt: Int = issueBlockParams.map(_.StaCnt).sum
57
58  def StdCnt: Int = issueBlockParams.map(_.StdCnt).sum
59
60  def MouCnt: Int = issueBlockParams.map(_.MouCnt).sum
61
62  def VipuCnt: Int = issueBlockParams.map(_.VipuCnt).sum
63
64  def VfpuCnt: Int = issueBlockParams.map(_.VfpuCnt).sum
65
66  def VlduCnt: Int = issueBlockParams.map(_.VlduCnt).sum
67
68  def VstuCnt: Int = issueBlockParams.map(_.VstuCnt).sum
69
70  def numExu: Int = issueBlockParams.map(_.exuBlockParams.size).sum
71
72  def hasCSR = CsrCnt > 0
73
74  def hasFence = FenceCnt > 0
75
76  def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum
77
78  def numWriteFpRf: Int = issueBlockParams.map(_.numWriteFpRf).sum
79
80  def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum
81
82  def numWriteVfRf: Int = issueBlockParams.map(_.numWriteVfRf).sum
83
84  def numNoDataWB: Int = issueBlockParams.map(_.numNoDataWB).sum
85
86  def numPcReadPort = {
87    val bjIssueQueues = issueBlockParams.filter(x => (x.JmpCnt + x.BrhCnt + x.FenceCnt) > 0)
88    if (bjIssueQueues.map(x => x.numEnq).sum > 0) numUopIn else 0
89  }
90
91  def needSrcFrm: Boolean = issueBlockParams.map(_.needSrcFrm).reduce(_ || _)
92
93  def numRedirect: Int = issueBlockParams.map(_.numRedirect).sum
94
95  def pregIdxWidth: Int = log2Up(numPregs)
96
97  def numWakeupFromWB: Int = schdType match {
98    case IntScheduler() | VfScheduler() => 8
99    case MemScheduler() => 16 // Todo
100    case _ => 0
101  }
102
103  def numIntRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numIntSrc).sum).sum
104
105  def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(x => x.numFpSrc + x.numVecSrc).sum).sum
106
107  // Todo: 14R8W
108  def numIntRfRead: Int = numIntRfReadByExu
109
110  def bindBackendParam(param: BackendParams): Unit = {
111    backendParam = param
112  }
113
114  def genExuInputBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = {
115    MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledBundle))
116  }
117
118  def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = {
119    MixedVec(this.issueBlockParams.map(_.genExuOutputDecoupledBundle))
120  }
121
122  def genExuOutputValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuOutput]]] = {
123    MixedVec(this.issueBlockParams.map(_.genExuOutputValidBundle))
124  }
125
126  def genExuBypassValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuBypassBundle]]] = {
127    MixedVec(this.issueBlockParams.map(_.genExuBypassValidBundle))
128  }
129
130  def wakeUpInExuSources: Seq[WakeUpSource] = {
131    SeqUtils.distinctBy(
132      issueBlockParams
133        .flatMap(_.wakeUpInExuSources)
134    )(_.name)
135  }
136
137  def wakeUpOutExuSources: Seq[WakeUpSource] = {
138    SeqUtils.distinctBy(
139      issueBlockParams
140        .flatMap(_.wakeUpOutExuSources)
141    )(_.name)
142  }
143
144  def genIQWakeUpInValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = {
145    MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam))))
146  }
147
148  def genIQWakeUpOutValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = {
149    MixedVec(this.wakeUpOutExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam))))
150  }
151
152  def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = {
153    val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match {
154      case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq
155      case _ => Seq()
156    }
157    val vfBundle = schdType match {
158      case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq
159      case _ => Seq()
160    }
161    MixedVec(intBundle ++ vfBundle)
162  }
163
164  // cfgs(issueIdx)(exuIdx)(set of exu's wb)
165  def getWbCfgs: Seq[Seq[Set[WbConfig]]] = {
166    this.issueBlockParams.map(_.getWbCfgs)
167  }
168}
169