xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision fd490615892783f3d997c6c4d5827fd793ddf832) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.issue.EntryBundles._
12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
13import xiangshan.backend.datapath.DataConfig._
14import xiangshan.backend.datapath.DataSource
15import xiangshan.backend.fu.{FuConfig, FuType}
16import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr}
17import xiangshan.backend.rob.RobPtr
18import xiangshan.backend.datapath.NewPipelineConnect
19import xiangshan.backend.fu.vector.Bundles.VSew
20
21class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
22  override def shouldBeInlined: Boolean = false
23
24  implicit val iqParams = params
25  lazy val module: IssueQueueImp = iqParams.schdType match {
26    case IntScheduler() => new IssueQueueIntImp(this)
27    case VfScheduler() => new IssueQueueVfImp(this)
28    case MemScheduler() =>
29      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
30      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
31      else new IssueQueueIntImp(this)
32    case _ => null
33  }
34}
35
36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
37  val empty = Output(Bool())
38  val full = Output(Bool())
39  val validCnt = Output(UInt(log2Ceil(numEntries).W))
40  val leftVec = Output(Vec(numEnq + 1, Bool()))
41}
42
43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
44
45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
46  // Inputs
47  val flush = Flipped(ValidIO(new Redirect))
48  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
49
50  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
51  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
52  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
53  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
54  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
55  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
56  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
57  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
58  val og0Cancel = Input(ExuOH(backendParams.numExu))
59  val og1Cancel = Input(ExuOH(backendParams.numExu))
60  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
61
62  // Outputs
63  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
64  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
65  val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W)))
66  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
67
68  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
69  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
70}
71
72class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
73  extends LazyModuleImp(wrapper)
74  with HasXSParameter {
75
76  override def desiredName: String = s"${params.getIQName}"
77
78  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
79    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
80    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
81    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " +
82    s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " +
83    s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}")
84
85  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
86  require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports")
87  require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq")
88  require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq")
89
90  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
91  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
92  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
93  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
94  val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap)
95
96  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}")
97  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
98  lazy val io = IO(new IssueQueueIO())
99
100  // Modules
101  val entries = Module(new Entries)
102  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
103  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
104  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
105  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
106  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
107  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
108
109  class WakeupQueueFlush extends Bundle {
110    val redirect = ValidIO(new Redirect)
111    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
112    val og0Fail = Output(Bool())
113    val og1Fail = Output(Bool())
114  }
115
116  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
117    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
118    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
119    val ogFailFlush = stage match {
120      case 1 => flush.og0Fail
121      case 2 => flush.og1Fail
122      case _ => false.B
123    }
124    redirectFlush || loadDependencyFlush || ogFailFlush
125  }
126
127  private def modificationFunc(exuInput: ExuInput): ExuInput = {
128    val newExuInput = WireDefault(exuInput)
129    newExuInput.loadDependency match {
130      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
131      case None =>
132    }
133    newExuInput
134  }
135
136  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
137    val lastExuInput = WireDefault(exuInput)
138    val newExuInput = WireDefault(newInput)
139    newExuInput.elements.foreach { case (name, data) =>
140      if (lastExuInput.elements.contains(name)) {
141        data := lastExuInput.elements(name)
142      }
143    }
144    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
145      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
146    }
147    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
148      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
149    }
150    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
151      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
152    }
153    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
154      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
155    }
156    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
157      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
158    }
159    newExuInput
160  }
161
162  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module(
163    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
164  ))}
165  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
166
167  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
168  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
169  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
170  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
171  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
172  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
173  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
174  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
175  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
176  val s0_enqValidVec = io.enq.map(_.valid)
177  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
178  val s0_enqNotFlush = !io.flush.valid
179  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
180  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
181
182
183  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
184  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
185
186  val validVec = VecInit(entries.io.valid.asBools)
187  val canIssueVec = VecInit(entries.io.canIssue.asBools)
188  dontTouch(canIssueVec)
189  val deqFirstIssueVec = entries.io.isFirstIssue
190
191  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
192  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
193  val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency
194  val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency)))
195  // (entryIdx)(srcIdx)(exuIdx)
196  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
197  val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer
198
199  // (deqIdx)(srcIdx)(exuIdx)
200  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
201  val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
202
203  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
204  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
205  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
206  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
207
208  //deq
209  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
210  val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W)))))
211  val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W)))))
212  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
213  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
214  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
215  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
216
217  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
218  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
219  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
220
221  //trans
222  val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W))))
223  val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W))))
224  val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W))))
225  val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W))))
226  simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get))
227
228  /**
229    * Connection of [[entries]]
230    */
231  entries.io match { case entriesIO: EntriesIO =>
232    entriesIO.flush                                             := io.flush
233    entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) =>
234      enq.valid                                                 := s0_doEnqSelValidVec(enqIdx)
235      enq.bits.status.robIdx                                    := s0_enqBits(enqIdx).robIdx
236      enq.bits.status.fuType                                    := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType))
237      val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size)
238      for(j <- 0 until numLsrc) {
239        enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
240        enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
241        enq.bits.status.srcStatus(j).srcState                   := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel)
242        enq.bits.status.srcStatus(j).dataSources.value          := Mux(
243          SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U),
244          DataSource.zero,
245          Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg)
246        )
247        enq.bits.status.srcStatus(j).srcLoadDependency          := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1))
248        if(params.hasIQWakeUp) {
249          enq.bits.status.srcStatus(j).srcTimer.get             := 0.U(3.W)
250          enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get     := 0.U.asTypeOf(ExuVec())
251        }
252      }
253      enq.bits.status.blocked                                   := false.B
254      enq.bits.status.issued                                    := false.B
255      enq.bits.status.firstIssue                                := false.B
256      enq.bits.status.issueTimer                                := "b10".U
257      enq.bits.status.deqPortIdx                                := 0.U
258      if (params.inIntSchd && params.AluCnt > 0) {
259        // dirty code for lui+addi(w) fusion
260        val isLuiAddiFusion = s0_enqBits(enqIdx).isLUI32
261        val luiImm = Cat(s0_enqBits(enqIdx).lsrc(1), s0_enqBits(enqIdx).lsrc(0), s0_enqBits(enqIdx).imm(ImmUnion.maxLen - 1, 0))
262        enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(enqIdx).imm))
263      }
264      else if (params.isLdAddrIQ || params.isHyAddrIQ) {
265        // dirty code for fused_lui_load
266        val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(enqIdx).srcType(0)) && FuType.isLoad(s0_enqBits(enqIdx).fuType)
267        enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(enqIdx)), s0_enqBits(enqIdx).imm))
268      }
269      else {
270        enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm)
271      }
272      enq.bits.payload                                          := s0_enqBits(enqIdx)
273    }
274    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
275      og0Resp                                                   := io.og0Resp(i)
276    }
277    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
278      og1Resp                                                   := io.og1Resp(i)
279    }
280    if (params.isLdAddrIQ || params.isHyAddrIQ) {
281      entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) =>
282        finalIssueResp                                          := io.finalIssueResp.get(i)
283      }
284      entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
285        memAddrIssueResp                                        := io.memAddrIssueResp.get(i)
286      }
287    }
288    for(deqIdx <- 0 until params.numDeq) {
289      entriesIO.deqReady(deqIdx)                                := deqBeforeDly(deqIdx).ready
290      entriesIO.deqSelOH(deqIdx).valid                          := deqSelValidVec(deqIdx)
291      entriesIO.deqSelOH(deqIdx).bits                           := deqSelOHVec(deqIdx)
292      entriesIO.enqEntryOldestSel(deqIdx)                       := enqEntryOldestSel(deqIdx)
293      entriesIO.simpEntryOldestSel.foreach(_(deqIdx)            := simpEntryOldestSel.get(deqIdx))
294      entriesIO.compEntryOldestSel.foreach(_(deqIdx)            := compEntryOldestSel.get(deqIdx))
295      entriesIO.othersEntryOldestSel.foreach(_(deqIdx)          := othersEntryOldestSel(deqIdx))
296      entriesIO.subDeqRequest.foreach(_(deqIdx)                 := subDeqRequest.get)
297      entriesIO.subDeqSelOH.foreach(_(deqIdx)                   := subDeqSelOHVec.get(deqIdx))
298    }
299    entriesIO.wakeUpFromWB                                      := io.wakeupFromWB
300    entriesIO.wakeUpFromIQ                                      := io.wakeupFromIQ
301    entriesIO.og0Cancel                                         := io.og0Cancel
302    entriesIO.og1Cancel                                         := io.og1Cancel
303    entriesIO.ldCancel                                          := io.ldCancel
304    entriesIO.simpEntryDeqSelVec.foreach(_                      := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits)))
305    //output
306    fuTypeVec                                                   := entriesIO.fuType
307    deqEntryVec                                                 := entriesIO.deqEntry
308    cancelDeqVec                                                := entriesIO.cancelDeqVec
309    simpEntryEnqSelVec.foreach(_                                := entriesIO.simpEntryEnqSelVec.get)
310    compEntryEnqSelVec.foreach(_                                := entriesIO.compEntryEnqSelVec.get)
311    othersEntryEnqSelVec.foreach(_                              := entriesIO.othersEntryEnqSelVec.get)
312  }
313
314
315  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
316
317  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
318    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
319  ).reverse)
320
321  // if deq port can accept the uop
322  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
323    Cat(fuTypeVec.map(fuType =>
324      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
325    ).reverse)
326  }
327
328  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
329    fuTypeVec.map(fuType =>
330      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
331  }
332
333  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
334    val mergeFuBusy = {
335      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
336      else canIssueVec.asUInt
337    }
338    val mergeIntWbBusy = {
339      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
340      else mergeFuBusy
341    }
342    val mergeVfWbBusy = {
343      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
344      else mergeIntWbBusy
345    }
346    merge := mergeVfWbBusy
347  }
348
349  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
350    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
351  }
352  dontTouch(fuTypeVec)
353  dontTouch(canIssueMergeAllBusy)
354  dontTouch(deqCanIssue)
355
356  if (params.numDeq == 2) {
357    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
358  }
359
360  if (params.numDeq == 2 && params.deqFuSame) {
361    val subDeqPolicy = Module(new DeqPolicy())
362
363    enqEntryOldestSel := DontCare
364
365    if (params.isAllComp || params.isAllSimp) {
366      othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
367        enq = othersEntryEnqSelVec.get,
368        canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
369      )
370      othersEntryOldestSel(1) := DontCare
371
372      subDeqPolicy.io.request := subDeqRequest.get
373      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
374      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
375    }
376    else {
377      simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq)
378      simpAgeDetectRequest.get(1) := DontCare
379      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
380      if (params.numEnq == 2) {
381        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
382      }
383
384      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
385        enq = simpEntryEnqSelVec.get,
386        canIssue = simpAgeDetectRequest.get
387      )
388
389      compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp,
390        enq = compEntryEnqSelVec.get,
391        canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp)
392      )
393      compEntryOldestSel.get(1) := DontCare
394
395      othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid
396      othersEntryOldestSel(0).bits := Cat(
397        compEntryOldestSel.get(0).bits,
398        Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits,
399      )
400      othersEntryOldestSel(1) := DontCare
401
402      subDeqPolicy.io.request := Reverse(subDeqRequest.get)
403      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
404      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits))
405    }
406
407    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
408
409    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
410    deqSelValidVec(1) := subDeqSelValidVec.get(0)
411    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
412                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
413                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
414    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
415
416    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
417      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
418      selOH := deqOH
419    }
420  }
421  else {
422    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
423      enq = VecInit(s0_doEnqSelValidVec),
424      canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0)))
425    )
426
427    if (params.isAllComp || params.isAllSimp) {
428      othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
429        enq = othersEntryEnqSelVec.get,
430        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq)))
431      )
432
433      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
434        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
435          selValid := false.B
436          selOH := 0.U.asTypeOf(selOH)
437        } else {
438          selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
439          selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
440        }
441      }
442    }
443    else {
444      othersEntryOldestSel := DontCare
445
446      deqCanIssue.zipWithIndex.foreach { case (req, i) =>
447        simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq)
448      }
449      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
450      if (params.numEnq == 2) {
451        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
452      }
453
454      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
455        enq = simpEntryEnqSelVec.get,
456        canIssue = simpAgeDetectRequest.get
457      )
458
459      compEntryOldestSel.get := AgeDetector(numEntries = params.numComp,
460        enq = compEntryEnqSelVec.get,
461        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp)))
462      )
463
464      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
465        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
466          selValid := false.B
467          selOH := 0.U.asTypeOf(selOH)
468        } else {
469          selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid
470          selOH := Cat(
471            compEntryOldestSel.get(i).bits,
472            Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits,
473            Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits
474          )
475        }
476      }
477    }
478
479    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
480      selValid := deqValid && deqBeforeDly(i).ready
481      selOH := deqOH
482    }
483  }
484
485  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
486
487  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
488    deqResp.valid := finalDeqSelValidVec(i)
489    deqResp.bits.resp   := RespType.success
490    deqResp.bits.robIdx := DontCare
491    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
492    deqResp.bits.uopIdx.foreach(_ := DontCare)
493  }
494
495  //fuBusyTable
496  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
497    if(busyTableWrite.nonEmpty) {
498      val btwr = busyTableWrite.get
499      val btrd = busyTableRead.get
500      btwr.io.in.deqResp := toBusyTableDeqResp(i)
501      btwr.io.in.og0Resp := io.og0Resp(i)
502      btwr.io.in.og1Resp := io.og1Resp(i)
503      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
504      btrd.io.in.fuTypeRegVec := fuTypeVec
505      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
506    }
507    else {
508      fuBusyTableMask(i) := 0.U(params.numEntries.W)
509    }
510  }
511
512  //wbfuBusyTable write
513  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
514    if(busyTableWrite.nonEmpty) {
515      val btwr = busyTableWrite.get
516      val bt = busyTable.get
517      val dq = deqResp.get
518      btwr.io.in.deqResp := toBusyTableDeqResp(i)
519      btwr.io.in.og0Resp := io.og0Resp(i)
520      btwr.io.in.og1Resp := io.og1Resp(i)
521      bt := btwr.io.out.fuBusyTable
522      dq := btwr.io.out.deqRespSet
523    }
524  }
525
526  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
527    if (busyTableWrite.nonEmpty) {
528      val btwr = busyTableWrite.get
529      val bt = busyTable.get
530      val dq = deqResp.get
531      btwr.io.in.deqResp := toBusyTableDeqResp(i)
532      btwr.io.in.og0Resp := io.og0Resp(i)
533      btwr.io.in.og1Resp := io.og1Resp(i)
534      bt := btwr.io.out.fuBusyTable
535      dq := btwr.io.out.deqRespSet
536    }
537  }
538
539  //wbfuBusyTable read
540  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
541    if(busyTableRead.nonEmpty) {
542      val btrd = busyTableRead.get
543      val bt = busyTable.get
544      btrd.io.in.fuBusyTable := bt
545      btrd.io.in.fuTypeRegVec := fuTypeVec
546      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
547    }
548    else {
549      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
550    }
551  }
552  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
553    if (busyTableRead.nonEmpty) {
554      val btrd = busyTableRead.get
555      val bt = busyTable.get
556      btrd.io.in.fuBusyTable := bt
557      btrd.io.in.fuTypeRegVec := fuTypeVec
558      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
559    }
560    else {
561      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
562    }
563  }
564
565  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
566    wakeUpQueueOption.foreach {
567      wakeUpQueue =>
568        val flush = Wire(new WakeupQueueFlush)
569        flush.redirect := io.flush
570        flush.ldCancel := io.ldCancel
571        flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp)
572        flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp)
573        wakeUpQueue.io.flush := flush
574        wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid
575        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
576        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
577        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
578    }
579  }
580
581  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
582    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
583    deq.bits.addrOH          := finalDeqSelOHVec(i)
584    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
585    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
586    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
587    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
588    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
589    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
590    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
591    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
592    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
593    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
594
595    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
596    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
597    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
598    deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i))
599    deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i))
600    deq.bits.common.src := DontCare
601    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
602
603    deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) =>
604      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
605      rf.foreach(_.addr := psrc)
606      rf.foreach(_.srcType := srcType)
607    }
608    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) =>
609      sink := source
610    }
611    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
612    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
613
614    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
615    deq.bits.common.perfDebugInfo.selectTime := GTimer()
616    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
617  }
618
619  private val deqShift = WireDefault(deqBeforeDly)
620  deqShift.zip(deqBeforeDly).foreach {
621    case (shifted, original) =>
622      original.ready := shifted.ready // this will not cause combinational loop
623      shifted.bits.common.loadDependency.foreach(
624        _ := original.bits.common.loadDependency.get.map(_ << 1)
625      )
626  }
627  io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) =>
628    NewPipelineConnect(
629      deq, deqDly, deqDly.valid,
630      false.B,
631      Option("Scheduler2DataPathPipe")
632    )
633  }
634  if(backendParams.debugEn) {
635    dontTouch(io.deqDelay)
636  }
637  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
638    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
639      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
640      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
641      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
642      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
643    } else if (wakeUpQueues(i).nonEmpty) {
644      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
645      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
646      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
647      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
648    } else {
649      wakeup.valid := false.B
650      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
651      wakeup.bits.is0Lat :=  0.U
652    }
653    if (wakeUpQueues(i).nonEmpty) {
654      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
655      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
656      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
657    }
658
659    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
660      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
661    }
662    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
663      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
664    }
665    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
666      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
667    }
668    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
669      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
670    }
671    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
672      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
673    }
674  }
675
676  // Todo: better counter implementation
677  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
678  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
679  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
680  private val enqEntryValidCntDeq0 = PopCount(
681    validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b }
682  )
683  private val othersValidCntDeq0 = PopCount(
684    validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b }
685  )
686  private val enqEntryValidCntDeq1 = PopCount(
687    validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b }
688  )
689  private val othersValidCntDeq1 = PopCount(
690    validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b }
691  )
692  protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
693    io.enq.map(_.bits.fuType).map(fuType =>
694      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
695  }
696  protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b })
697  protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b })
698  io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0)
699  io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1)
700  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
701  for (i <- 0 until params.numEnq) {
702    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
703  }
704  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
705  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
706    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
707  }
708  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
709  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
710
711  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
712  io.status.empty := !Cat(validVec).orR
713  io.status.full := othersCanotIn
714  io.status.validCnt := PopCount(validVec)
715
716  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
717    Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
718  }
719
720  // issue perf counter
721  // enq count
722  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
723  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
724  XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) }))
725  XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) }))
726  XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire))
727  XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire))
728  // valid count
729  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
730  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
731  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
732  // only split when more than 1 func type
733  if (params.getFuCfgs.size > 0) {
734    for (t <- FuType.functionNameMap.keys) {
735      val fuName = FuType.functionNameMap(t)
736      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
737        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
738      }
739    }
740  }
741  // ready instr count
742  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
743  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
744  // only split when more than 1 func type
745  if (params.getFuCfgs.size > 0) {
746    for (t <- FuType.functionNameMap.keys) {
747      val fuName = FuType.functionNameMap(t)
748      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
749        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
750      }
751    }
752  }
753
754  // deq instr count
755  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
756  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
757  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
758  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
759
760  // deq instr data source count
761  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
762    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
763  }.reduce(_ +& _))
764  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
765    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
766  }.reduce(_ +& _))
767  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
768    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
769  }.reduce(_ +& _))
770  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
771    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
772  }.reduce(_ +& _))
773
774  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
775    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
776  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
777  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
778    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
779  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
780  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
781    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
782  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
783  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
784    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
785  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
786
787  // deq instr data source count for each futype
788  for (t <- FuType.functionNameMap.keys) {
789    val fuName = FuType.functionNameMap(t)
790    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
791      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
792        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
793      }.reduce(_ +& _))
794      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
795        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
796      }.reduce(_ +& _))
797      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
798        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
799      }.reduce(_ +& _))
800      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
801        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
802      }.reduce(_ +& _))
803
804      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
805        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
806      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
807      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
808        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
809      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
810      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
811        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
812      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
813      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
814        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
815      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
816    }
817  }
818
819  // cancel instr count
820  if (params.hasIQWakeUp) {
821    val cancelVec: Vec[Bool] = entries.io.cancel.get
822    XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)))
823    XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1)
824    for (t <- FuType.functionNameMap.keys) {
825      val fuName = FuType.functionNameMap(t)
826      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
827        XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }))
828        XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1)
829      }
830    }
831  }
832}
833
834class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
835  val fastMatch = UInt(backendParams.LduCnt.W)
836  val fastImm = UInt(12.W)
837}
838
839class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
840
841class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
842  extends IssueQueueImp(wrapper)
843{
844  io.suggestName("none")
845  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
846
847  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
848    deq.bits.common.pc.foreach(_ := DontCare)
849    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
850    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
851    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
852    deq.bits.common.predictInfo.foreach(x => {
853      x.target := DontCare
854      x.taken := deqEntryVec(i).bits.payload.pred_taken
855    })
856    // for std
857    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
858    // for i2f
859    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
860  }}
861}
862
863class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
864  extends IssueQueueImp(wrapper)
865{
866  s0_enqBits.foreach{ x =>
867    x.srcType(3) := SrcType.vp // v0: mask src
868    x.srcType(4) := SrcType.vp // vl&vtype
869  }
870  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
871    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
872    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
873    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
874    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
875  }}
876}
877
878class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
879  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ)))
880
881  // TODO: is still needed?
882  val checkWait = new Bundle {
883    val stIssuePtr = Input(new SqPtr)
884    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
885  }
886  val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle))
887
888  // load wakeup
889  val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst())))
890
891  // vector
892  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
893  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
894}
895
896class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
897  val memIO = Some(new IssueQueueMemBundle)
898}
899
900class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
901  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
902
903  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
904    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
905  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
906
907  io.suggestName("none")
908  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
909  private val memIO = io.memIO.get
910
911  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
912
913  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
914    slowResp.valid       := memIO.feedbackIO(i).feedbackSlow.valid
915    slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
916    slowResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
917    slowResp.bits.fuType := DontCare
918  }
919
920  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
921    fastResp.valid       := memIO.feedbackIO(i).feedbackFast.valid
922    fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx
923    fastResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
924    fastResp.bits.fuType := DontCare
925  }
926
927  // load wakeup
928  val loadWakeUpIter = memIO.loadWakeUp.iterator
929  io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) =>
930    if (param.hasLoadExu) {
931      require(wakeUpQueues(i).isEmpty)
932      val uop = loadWakeUpIter.next()
933
934      wakeup.valid := GatedValidRegNext(uop.fire)
935      wakeup.bits.rfWen  := GatedValidRegNext(uop.bits.rfWen  && uop.fire)
936      wakeup.bits.fpWen  := GatedValidRegNext(uop.bits.fpWen  && uop.fire)
937      wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire)
938      wakeup.bits.pdest  := RegEnable(uop.bits.pdest, uop.fire)
939      wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only
940
941      wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen  && uop.fire)))
942      wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen  && uop.fire)))
943      wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire)))
944      wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire)))
945      wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only
946
947      wakeup.bits.is0Lat := 0.U
948    }
949  }
950  require(!loadWakeUpIter.hasNext)
951
952  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
953    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
954    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
955    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
956    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
957    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
958    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
959    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
960    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
961    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
962  }
963}
964
965class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
966  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
967
968  require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
969  println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}")
970
971  io.suggestName("none")
972  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
973  private val memIO = io.memIO.get
974
975  require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports")
976
977  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
978    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
979    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
980      (if (j < i) !valid(j) || compareVec(i)(j)
981      else if (j == i) valid(i)
982      else !valid(j) || !compareVec(j)(i))
983    )).andR))
984    resultOnehot
985  }
986
987  val robIdxVec = entries.io.robIdx.get
988  val uopIdxVec = entries.io.uopIdx.get
989  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
990
991  deqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
992  deqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
993  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR && deqBeforeDly.head.ready
994  finalDeqSelOHVec.head := deqSelOHVec.head
995
996  s0_enqBits.foreach{ x =>
997    x.srcType(3) := SrcType.vp // v0: mask src
998    x.srcType(4) := SrcType.vp // vl&vtype
999  }
1000
1001  for (i <- entries.io.enq.indices) {
1002    entries.io.enq(i).bits.status match { case enqData =>
1003      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
1004      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
1005      // MemAddrIQ also handle vector insts
1006      enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem
1007      // update blocked
1008      val isLsqHead = {
1009        s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get &&
1010        s0_enqBits(i).sqIdx <= memIO.sqDeqPtr.get
1011      }
1012      enqData.blocked          := !isLsqHead
1013    }
1014  }
1015
1016  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
1017    slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
1018    slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
1019    slowResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
1020    slowResp.bits.fuType           := DontCare
1021    slowResp.bits.uopIdx.get       := memIO.feedbackIO(i).feedbackSlow.bits.uopIdx.get
1022  }
1023
1024  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1025    fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
1026    fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1027    fastResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1028    fastResp.bits.fuType           := DontCare
1029    fastResp.bits.uopIdx.get       := memIO.feedbackIO(i).feedbackFast.bits.uopIdx.get
1030  }
1031
1032  entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get
1033  entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get
1034
1035  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1036    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx)
1037    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx)
1038    deq.bits.common.numLsElem.get := deqEntryVec(i).bits.status.vecMem.get.numLsElem
1039    deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem)
1040    if (params.isVecLduIQ) {
1041      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
1042      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
1043    }
1044    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1045    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1046    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1047    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1048  }
1049}
1050