1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne, GatedValidRegNext} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case VfScheduler() => new IssueQueueVfImp(this) 27 case MemScheduler() => 28 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 29 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 30 else new IssueQueueIntImp(this) 31 case _ => null 32 } 33} 34 35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 36 val empty = Output(Bool()) 37 val full = Output(Bool()) 38 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 39 val leftVec = Output(Vec(numEnq + 1, Bool())) 40} 41 42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 43 44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 45 // Inputs 46 val flush = Flipped(ValidIO(new Redirect)) 47 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 48 49 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 50 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 52 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 55 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 56 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 57 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 58 val og0Cancel = Input(ExuOH(backendParams.numExu)) 59 val og1Cancel = Input(ExuOH(backendParams.numExu)) 60 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 61 62 // Outputs 63 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 64 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 65 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 66 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 67 68 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 69 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 70} 71 72class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 73 extends LazyModuleImp(wrapper) 74 with HasXSParameter { 75 76 override def desiredName: String = s"${params.getIQName}" 77 78 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 79 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 80 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 81 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 82 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 83 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 84 85 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 86 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 87 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 88 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 89 90 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 91 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 92 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 93 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 94 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 95 96 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 97 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 98 lazy val io = IO(new IssueQueueIO()) 99 100 // Modules 101 val entries = Module(new Entries) 102 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 103 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 104 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 105 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 106 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 107 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 108 109 class WakeupQueueFlush extends Bundle { 110 val redirect = ValidIO(new Redirect) 111 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 112 val og0Fail = Output(Bool()) 113 val og1Fail = Output(Bool()) 114 } 115 116 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 117 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 118 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 119 val ogFailFlush = stage match { 120 case 1 => flush.og0Fail 121 case 2 => flush.og1Fail 122 case _ => false.B 123 } 124 redirectFlush || loadDependencyFlush || ogFailFlush 125 } 126 127 private def modificationFunc(exuInput: ExuInput): ExuInput = { 128 val newExuInput = WireDefault(exuInput) 129 newExuInput.loadDependency match { 130 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 131 case None => 132 } 133 newExuInput 134 } 135 136 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 137 val lastExuInput = WireDefault(exuInput) 138 val newExuInput = WireDefault(newInput) 139 newExuInput.elements.foreach { case (name, data) => 140 if (lastExuInput.elements.contains(name)) { 141 data := lastExuInput.elements(name) 142 } 143 } 144 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 145 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 146 } 147 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 148 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 149 } 150 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 151 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 152 } 153 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 154 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 155 } 156 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 157 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 158 } 159 newExuInput 160 } 161 162 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 163 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 164 ))} 165 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 166 167 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 168 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 169 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 170 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 171 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 172 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 173 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 174 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 175 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 176 val s0_enqValidVec = io.enq.map(_.valid) 177 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 178 val s0_enqNotFlush = !io.flush.valid 179 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 180 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 181 182 183 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 184 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 185 186 val validVec = VecInit(entries.io.valid.asBools) 187 val canIssueVec = VecInit(entries.io.canIssue.asBools) 188 dontTouch(canIssueVec) 189 val deqFirstIssueVec = entries.io.isFirstIssue 190 191 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 192 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 193 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 194 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 195 // (entryIdx)(srcIdx)(exuIdx) 196 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 197 // (deqIdx)(srcIdx)(exuIdx) 198 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 199 200 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 201 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 202 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 203 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 204 205 //deq 206 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 207 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 208 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 209 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 210 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 211 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 212 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 213 214 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 215 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 216 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 217 218 //trans 219 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 220 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 221 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 222 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 223 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 224 225 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 226 // as vf exu's min latency is 1, we do not need consider og0cancel 227 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 228 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 229 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 230 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 231 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 232 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 233 } else { 234 w := w_src 235 } 236 } 237 238 /** 239 * Connection of [[entries]] 240 */ 241 entries.io match { case entriesIO: EntriesIO => 242 entriesIO.flush := io.flush 243 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 244 enq.valid := s0_doEnqSelValidVec(enqIdx) 245 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 246 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 247 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 248 for(j <- 0 until numLsrc) { 249 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 250 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 251 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 252 enq.bits.status.srcStatus(j).dataSources.value := Mux( 253 SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 254 DataSource.zero, 255 Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg) 256 ) 257 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1)) 258 if(params.hasIQWakeUp) { 259 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 260 } 261 } 262 enq.bits.status.blocked := false.B 263 enq.bits.status.issued := false.B 264 enq.bits.status.firstIssue := false.B 265 enq.bits.status.issueTimer := "b11".U 266 enq.bits.status.deqPortIdx := 0.U 267 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 268 enq.bits.payload := s0_enqBits(enqIdx) 269 } 270 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 271 og0Resp := io.og0Resp(i) 272 } 273 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 274 og1Resp := io.og1Resp(i) 275 } 276 if (params.inVfSchd) { 277 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 278 og2Resp := io.og2Resp.get(i) 279 } 280 } 281 if (params.isLdAddrIQ || params.isHyAddrIQ) { 282 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 283 finalIssueResp := io.finalIssueResp.get(i) 284 } 285 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 286 memAddrIssueResp := io.memAddrIssueResp.get(i) 287 } 288 } 289 for(deqIdx <- 0 until params.numDeq) { 290 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 291 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 292 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 293 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 294 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 295 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 296 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 297 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 298 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 299 } 300 entriesIO.wakeUpFromWB := io.wakeupFromWB 301 entriesIO.wakeUpFromIQ := wakeupFromIQ 302 entriesIO.og0Cancel := io.og0Cancel 303 entriesIO.og1Cancel := io.og1Cancel 304 entriesIO.ldCancel := io.ldCancel 305 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 306 //output 307 fuTypeVec := entriesIO.fuType 308 deqEntryVec := entriesIO.deqEntry 309 cancelDeqVec := entriesIO.cancelDeqVec 310 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 311 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 312 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 313 } 314 315 316 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 317 318 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 319 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 320 ).reverse) 321 322 // if deq port can accept the uop 323 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 324 Cat(fuTypeVec.map(fuType => 325 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 326 ).reverse) 327 } 328 329 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 330 fuTypeVec.map(fuType => 331 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 332 } 333 334 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 335 val mergeFuBusy = { 336 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 337 else canIssueVec.asUInt 338 } 339 val mergeIntWbBusy = { 340 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 341 else mergeFuBusy 342 } 343 val mergeVfWbBusy = { 344 if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i)) 345 else mergeIntWbBusy 346 } 347 merge := mergeVfWbBusy 348 } 349 350 deqCanIssue.zipWithIndex.foreach { case (req, i) => 351 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 352 } 353 dontTouch(fuTypeVec) 354 dontTouch(canIssueMergeAllBusy) 355 dontTouch(deqCanIssue) 356 357 if (params.numDeq == 2) { 358 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 359 } 360 361 if (params.numDeq == 2 && params.deqFuSame) { 362 val subDeqPolicy = Module(new DeqPolicy()) 363 364 enqEntryOldestSel := DontCare 365 366 if (params.isAllComp || params.isAllSimp) { 367 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 368 enq = othersEntryEnqSelVec.get, 369 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 370 ) 371 othersEntryOldestSel(1) := DontCare 372 373 subDeqPolicy.io.request := subDeqRequest.get 374 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 375 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 376 } 377 else { 378 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 379 simpAgeDetectRequest.get(1) := DontCare 380 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 381 if (params.numEnq == 2) { 382 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 383 } 384 385 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 386 enq = simpEntryEnqSelVec.get, 387 canIssue = simpAgeDetectRequest.get 388 ) 389 390 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 391 enq = compEntryEnqSelVec.get, 392 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 393 ) 394 compEntryOldestSel.get(1) := DontCare 395 396 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 397 othersEntryOldestSel(0).bits := Cat( 398 compEntryOldestSel.get(0).bits, 399 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 400 ) 401 othersEntryOldestSel(1) := DontCare 402 403 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 404 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 405 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 406 } 407 408 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 409 410 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 411 deqSelValidVec(1) := subDeqSelValidVec.get(0) 412 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 413 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 414 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 415 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 416 417 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 418 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 419 selOH := deqOH 420 } 421 } 422 else { 423 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 424 enq = VecInit(s0_doEnqSelValidVec), 425 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 426 ) 427 428 if (params.isAllComp || params.isAllSimp) { 429 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 430 enq = othersEntryEnqSelVec.get, 431 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 432 ) 433 434 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 435 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 436 selValid := false.B 437 selOH := 0.U.asTypeOf(selOH) 438 } else { 439 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 440 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 441 } 442 } 443 } 444 else { 445 othersEntryOldestSel := DontCare 446 447 deqCanIssue.zipWithIndex.foreach { case (req, i) => 448 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 449 } 450 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 451 if (params.numEnq == 2) { 452 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 453 } 454 455 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 456 enq = simpEntryEnqSelVec.get, 457 canIssue = simpAgeDetectRequest.get 458 ) 459 460 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 461 enq = compEntryEnqSelVec.get, 462 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 463 ) 464 465 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 466 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 467 selValid := false.B 468 selOH := 0.U.asTypeOf(selOH) 469 } else { 470 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 471 selOH := Cat( 472 compEntryOldestSel.get(i).bits, 473 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 474 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 475 ) 476 } 477 } 478 } 479 480 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 481 selValid := deqValid && deqBeforeDly(i).ready 482 selOH := deqOH 483 } 484 } 485 486 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 487 488 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 489 deqResp.valid := finalDeqSelValidVec(i) 490 deqResp.bits.resp := RespType.success 491 deqResp.bits.robIdx := DontCare 492 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 493 deqResp.bits.uopIdx.foreach(_ := DontCare) 494 } 495 496 //fuBusyTable 497 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 498 if(busyTableWrite.nonEmpty) { 499 val btwr = busyTableWrite.get 500 val btrd = busyTableRead.get 501 btwr.io.in.deqResp := toBusyTableDeqResp(i) 502 btwr.io.in.og0Resp := io.og0Resp(i) 503 btwr.io.in.og1Resp := io.og1Resp(i) 504 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 505 btrd.io.in.fuTypeRegVec := fuTypeVec 506 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 507 } 508 else { 509 fuBusyTableMask(i) := 0.U(params.numEntries.W) 510 } 511 } 512 513 //wbfuBusyTable write 514 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 515 if(busyTableWrite.nonEmpty) { 516 val btwr = busyTableWrite.get 517 val bt = busyTable.get 518 val dq = deqResp.get 519 btwr.io.in.deqResp := toBusyTableDeqResp(i) 520 btwr.io.in.og0Resp := io.og0Resp(i) 521 btwr.io.in.og1Resp := io.og1Resp(i) 522 bt := btwr.io.out.fuBusyTable 523 dq := btwr.io.out.deqRespSet 524 } 525 } 526 527 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 528 if (busyTableWrite.nonEmpty) { 529 val btwr = busyTableWrite.get 530 val bt = busyTable.get 531 val dq = deqResp.get 532 btwr.io.in.deqResp := toBusyTableDeqResp(i) 533 btwr.io.in.og0Resp := io.og0Resp(i) 534 btwr.io.in.og1Resp := io.og1Resp(i) 535 bt := btwr.io.out.fuBusyTable 536 dq := btwr.io.out.deqRespSet 537 } 538 } 539 540 //wbfuBusyTable read 541 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 542 if(busyTableRead.nonEmpty) { 543 val btrd = busyTableRead.get 544 val bt = busyTable.get 545 btrd.io.in.fuBusyTable := bt 546 btrd.io.in.fuTypeRegVec := fuTypeVec 547 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 548 } 549 else { 550 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 551 } 552 } 553 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 554 if (busyTableRead.nonEmpty) { 555 val btrd = busyTableRead.get 556 val bt = busyTable.get 557 btrd.io.in.fuBusyTable := bt 558 btrd.io.in.fuTypeRegVec := fuTypeVec 559 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 560 } 561 else { 562 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 563 } 564 } 565 566 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 567 wakeUpQueueOption.foreach { 568 wakeUpQueue => 569 val flush = Wire(new WakeupQueueFlush) 570 flush.redirect := io.flush 571 flush.ldCancel := io.ldCancel 572 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 573 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 574 wakeUpQueue.io.flush := flush 575 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 576 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 577 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 578 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 579 } 580 } 581 582 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 583 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 584 deq.bits.addrOH := finalDeqSelOHVec(i) 585 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 586 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 587 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 588 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 589 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 590 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 591 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 592 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 593 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 594 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 595 596 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 597 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 598 deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i)) 599 deq.bits.common.srcTimer.foreach(_ := DontCare) 600 deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i)) 601 deq.bits.common.src := DontCare 602 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 603 604 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 605 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 606 rf.foreach(_.addr := psrc) 607 rf.foreach(_.srcType := srcType) 608 } 609 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 610 sink := source 611 } 612 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 613 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 614 615 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 616 deq.bits.common.perfDebugInfo.selectTime := GTimer() 617 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 618 } 619 620 private val deqShift = WireDefault(deqBeforeDly) 621 deqShift.zip(deqBeforeDly).foreach { 622 case (shifted, original) => 623 original.ready := shifted.ready // this will not cause combinational loop 624 shifted.bits.common.loadDependency.foreach( 625 _ := original.bits.common.loadDependency.get.map(_ << 1) 626 ) 627 } 628 io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) => 629 NewPipelineConnect( 630 deq, deqDly, deqDly.valid, 631 false.B, 632 Option("Scheduler2DataPathPipe") 633 ) 634 } 635 if(backendParams.debugEn) { 636 dontTouch(io.deqDelay) 637 } 638 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 639 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 640 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 641 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 642 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 643 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 644 } else if (wakeUpQueues(i).nonEmpty) { 645 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 646 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 647 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 648 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 649 } else { 650 wakeup.valid := false.B 651 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 652 wakeup.bits.is0Lat := 0.U 653 } 654 if (wakeUpQueues(i).nonEmpty) { 655 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 656 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 657 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 658 } 659 660 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 661 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 662 } 663 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 664 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 665 } 666 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 667 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 668 } 669 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 670 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 671 } 672 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 673 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 674 } 675 } 676 677 // Todo: better counter implementation 678 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 679 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 680 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 681 private val enqEntryValidCntDeq0 = PopCount( 682 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 683 ) 684 private val othersValidCntDeq0 = PopCount( 685 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 686 ) 687 private val enqEntryValidCntDeq1 = PopCount( 688 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 689 ) 690 private val othersValidCntDeq1 = PopCount( 691 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 692 ) 693 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 694 io.enq.map(_.bits.fuType).map(fuType => 695 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 696 } 697 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 698 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 699 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 700 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 701 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 702 for (i <- 0 until params.numEnq) { 703 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 704 } 705 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 706 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 707 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 708 } 709 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 710 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 711 712 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 713 io.status.empty := !Cat(validVec).orR 714 io.status.full := othersCanotIn 715 io.status.validCnt := PopCount(validVec) 716 717 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 718 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 719 } 720 721 // issue perf counter 722 // enq count 723 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 724 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 725 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 726 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 727 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 728 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 729 // valid count 730 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 731 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 732 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 733 // only split when more than 1 func type 734 if (params.getFuCfgs.size > 0) { 735 for (t <- FuType.functionNameMap.keys) { 736 val fuName = FuType.functionNameMap(t) 737 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 738 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 739 } 740 } 741 } 742 // ready instr count 743 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 744 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 745 // only split when more than 1 func type 746 if (params.getFuCfgs.size > 0) { 747 for (t <- FuType.functionNameMap.keys) { 748 val fuName = FuType.functionNameMap(t) 749 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 750 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 751 } 752 } 753 } 754 755 // deq instr count 756 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 757 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 758 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 759 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 760 761 // deq instr data source count 762 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 763 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 764 }.reduce(_ +& _)) 765 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 766 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 767 }.reduce(_ +& _)) 768 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 769 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 770 }.reduce(_ +& _)) 771 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 772 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 773 }.reduce(_ +& _)) 774 775 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 776 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 777 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 778 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 779 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 780 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 781 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 782 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 783 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 784 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 785 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 786 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 787 788 // deq instr data source count for each futype 789 for (t <- FuType.functionNameMap.keys) { 790 val fuName = FuType.functionNameMap(t) 791 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 792 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 793 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 794 }.reduce(_ +& _)) 795 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 796 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 797 }.reduce(_ +& _)) 798 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 799 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 800 }.reduce(_ +& _)) 801 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 802 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 803 }.reduce(_ +& _)) 804 805 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 806 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 807 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 808 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 809 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 810 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 811 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 812 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 813 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 814 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 815 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 816 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 817 } 818 } 819} 820 821class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 822 val fastMatch = UInt(backendParams.LduCnt.W) 823 val fastImm = UInt(12.W) 824} 825 826class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 827 828class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 829 extends IssueQueueImp(wrapper) 830{ 831 io.suggestName("none") 832 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 833 834 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 835 deq.bits.common.pc.foreach(_ := DontCare) 836 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 837 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 838 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 839 deq.bits.common.predictInfo.foreach(x => { 840 x.target := DontCare 841 x.taken := deqEntryVec(i).bits.payload.pred_taken 842 }) 843 // for std 844 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 845 // for i2f 846 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 847 }} 848} 849 850class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 851 extends IssueQueueImp(wrapper) 852{ 853 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 854 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 855 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 856 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 857 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 858 }} 859} 860 861class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 862 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO)) 863 864 // TODO: is still needed? 865 val checkWait = new Bundle { 866 val stIssuePtr = Input(new SqPtr) 867 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 868 } 869 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 870 871 // load wakeup 872 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 873 874 // vector 875 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 876 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 877} 878 879class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 880 val memIO = Some(new IssueQueueMemBundle) 881} 882 883class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 884 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 885 886 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 887 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 888 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 889 890 io.suggestName("none") 891 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 892 private val memIO = io.memIO.get 893 894 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 895 896 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 897 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 898 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 899 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 900 slowResp.bits.fuType := DontCare 901 } 902 903 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 904 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 905 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 906 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 907 fastResp.bits.fuType := DontCare 908 } 909 910 // load wakeup 911 val loadWakeUpIter = memIO.loadWakeUp.iterator 912 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 913 if (param.hasLoadExu) { 914 require(wakeUpQueues(i).isEmpty) 915 val uop = loadWakeUpIter.next() 916 917 wakeup.valid := GatedValidRegNext(uop.fire) 918 wakeup.bits.rfWen := GatedValidRegNext(uop.bits.rfWen && uop.fire) 919 wakeup.bits.fpWen := GatedValidRegNext(uop.bits.fpWen && uop.fire) 920 wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire) 921 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 922 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 923 924 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen && uop.fire))) 925 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen && uop.fire))) 926 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire))) 927 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 928 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 929 930 wakeup.bits.is0Lat := 0.U 931 } 932 } 933 require(!loadWakeUpIter.hasNext) 934 935 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 936 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 937 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 938 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 939 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 940 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 941 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 942 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 943 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 944 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 945 } 946} 947 948class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 949 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 950 951 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 952 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 953 954 io.suggestName("none") 955 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 956 private val memIO = io.memIO.get 957 958 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 959 960 def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = { 961 val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j)))) 962 val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j => 963 (if (j < i) !valid(j) || compareVec(i)(j) 964 else if (j == i) valid(i) 965 else !valid(j) || !compareVec(j)(i)) 966 )).andR)) 967 resultOnehot 968 } 969 970 val robIdxVec = entries.io.robIdx.get 971 val uopIdxVec = entries.io.uopIdx.get 972 val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec) 973 974 deqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR 975 deqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt 976 finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR && deqBeforeDly.head.ready 977 finalDeqSelOHVec.head := deqSelOHVec.head 978 979 for (i <- entries.io.enq.indices) { 980 entries.io.enq(i).bits.status match { case enqData => 981 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 982 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 983 984 // update blocked 985 val isLsqHead = { 986 s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get && 987 s0_enqBits(i).sqIdx <= memIO.sqDeqPtr.get 988 } 989 enqData.blocked := !isLsqHead 990 } 991 } 992 993 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 994 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 995 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 996 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 997 slowResp.bits.fuType := DontCare 998 slowResp.bits.uopIdx.get := 0.U // Todo 999 } 1000 1001 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1002 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1003 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1004 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1005 fastResp.bits.fuType := DontCare 1006 fastResp.bits.uopIdx.get := 0.U // Todo 1007 } 1008 1009 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1010 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1011 1012 1013 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1014 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1015 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1016 if (params.isVecLduIQ) { 1017 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1018 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1019 } 1020 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1021 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1022 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1023 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1024 } 1025} 1026