1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case VfScheduler() => new IssueQueueVfImp(this) 27 case MemScheduler() => 28 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 29 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 30 else new IssueQueueIntImp(this) 31 case _ => null 32 } 33} 34 35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 36 val empty = Output(Bool()) 37 val full = Output(Bool()) 38 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 39 val leftVec = Output(Vec(numEnq + 1, Bool())) 40} 41 42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 43 44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 45 // Inputs 46 val flush = Flipped(ValidIO(new Redirect)) 47 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 48 49 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 50 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 52 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 54 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 55 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 56 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 57 val og0Cancel = Input(ExuOH(backendParams.numExu)) 58 val og1Cancel = Input(ExuOH(backendParams.numExu)) 59 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 60 61 // Outputs 62 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 63 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 64 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 65 66 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 67 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 68} 69 70class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 71 extends LazyModuleImp(wrapper) 72 with HasXSParameter { 73 74 override def desiredName: String = s"${params.getIQName}" 75 76 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 77 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 78 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 79 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 80 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 81 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 82 83 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 84 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 85 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 86 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 87 88 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 89 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 90 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 91 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 92 val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap) 93 94 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}") 95 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 96 lazy val io = IO(new IssueQueueIO()) 97 98 // Modules 99 val entries = Module(new Entries) 100 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 101 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 102 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 103 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 104 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 105 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 106 107 class WakeupQueueFlush extends Bundle { 108 val redirect = ValidIO(new Redirect) 109 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 110 val og0Fail = Output(Bool()) 111 val og1Fail = Output(Bool()) 112 } 113 114 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 115 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 116 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 117 val ogFailFlush = stage match { 118 case 1 => flush.og0Fail 119 case 2 => flush.og1Fail 120 case _ => false.B 121 } 122 redirectFlush || loadDependencyFlush || ogFailFlush 123 } 124 125 private def modificationFunc(exuInput: ExuInput): ExuInput = { 126 val newExuInput = WireDefault(exuInput) 127 newExuInput.loadDependency match { 128 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 129 case None => 130 } 131 newExuInput 132 } 133 134 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 135 val lastExuInput = WireDefault(exuInput) 136 val newExuInput = WireDefault(newInput) 137 newExuInput.elements.foreach { case (name, data) => 138 if (lastExuInput.elements.contains(name)) { 139 data := lastExuInput.elements(name) 140 } 141 } 142 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 143 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 144 } 145 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 146 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 147 } 148 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 149 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 150 } 151 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 152 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 153 } 154 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 155 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 156 } 157 newExuInput 158 } 159 160 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 161 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.fuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 162 ))} 163 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 164 165 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 166 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 167 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 168 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 169 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 170 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 171 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 172 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 173 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 174 val s0_enqValidVec = io.enq.map(_.valid) 175 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 176 val s0_enqNotFlush = !io.flush.valid 177 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 178 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 179 180 181 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 182 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 183 184 val validVec = VecInit(entries.io.valid.asBools) 185 val canIssueVec = VecInit(entries.io.canIssue.asBools) 186 dontTouch(canIssueVec) 187 val deqFirstIssueVec = entries.io.isFirstIssue 188 189 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 190 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 191 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 192 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 193 // (entryIdx)(srcIdx)(exuIdx) 194 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 195 val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer 196 197 // (deqIdx)(srcIdx)(exuIdx) 198 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 199 val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 200 201 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 202 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 203 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 204 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 206 //deq 207 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 208 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 209 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 210 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 211 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 212 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 213 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 214 215 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 216 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 217 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 218 219 //trans 220 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 221 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 222 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 223 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 224 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 225 226 /** 227 * Connection of [[entries]] 228 */ 229 entries.io match { case entriesIO: EntriesIO => 230 entriesIO.flush := io.flush 231 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 232 enq.valid := s0_doEnqSelValidVec(enqIdx) 233 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 234 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 235 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 236 for(j <- 0 until numLsrc) { 237 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 238 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 239 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 240 enq.bits.status.srcStatus(j).dataSources.value := DataSource.reg 241 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1)) 242 if(params.hasIQWakeUp) { 243 enq.bits.status.srcStatus(j).srcTimer.get := 0.U(3.W) 244 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 245 } 246 } 247 enq.bits.status.blocked := false.B 248 enq.bits.status.issued := false.B 249 enq.bits.status.firstIssue := false.B 250 enq.bits.status.issueTimer := "b10".U 251 enq.bits.status.deqPortIdx := 0.U 252 if (params.isVecMemIQ) { 253 enq.bits.status.vecMem.get.uopIdx := s0_enqBits(enqIdx).uopIdx 254 } 255 if (params.inIntSchd && params.AluCnt > 0) { 256 // dirty code for lui+addi(w) fusion 257 val isLuiAddiFusion = s0_enqBits(enqIdx).isLUI32 258 val luiImm = Cat(s0_enqBits(enqIdx).lsrc(1), s0_enqBits(enqIdx).lsrc(0), s0_enqBits(enqIdx).imm(ImmUnion.maxLen - 1, 0)) 259 enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(enqIdx).imm)) 260 } 261 else if (params.inMemSchd && params.LduCnt > 0) { 262 // dirty code for fused_lui_load 263 val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(enqIdx).srcType(0)) && FuType.isLoad(s0_enqBits(enqIdx).fuType) 264 enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(enqIdx)), s0_enqBits(enqIdx).imm)) 265 } 266 else { 267 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 268 } 269 enq.bits.payload := s0_enqBits(enqIdx) 270 } 271 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 272 og0Resp := io.og0Resp(i) 273 } 274 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 275 og1Resp := io.og1Resp(i) 276 } 277 entriesIO.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, i) => 278 finalIssueResp := io.finalIssueResp.get(i) 279 }) 280 for(deqIdx <- 0 until params.numDeq) { 281 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 282 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 283 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 284 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 285 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 286 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 287 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 288 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 289 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 290 } 291 entriesIO.wakeUpFromWB := io.wakeupFromWB 292 entriesIO.wakeUpFromIQ := io.wakeupFromIQ 293 entriesIO.og0Cancel := io.og0Cancel 294 entriesIO.og1Cancel := io.og1Cancel 295 entriesIO.ldCancel := io.ldCancel 296 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 297 //output 298 fuTypeVec := entriesIO.fuType 299 deqEntryVec := entriesIO.deqEntry 300 cancelDeqVec := entriesIO.cancelDeqVec 301 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 302 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 303 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 304 } 305 306 307 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 308 309 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 310 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 311 ).reverse) 312 313 // if deq port can accept the uop 314 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 315 Cat(fuTypeVec.map(fuType => 316 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 317 ).reverse) 318 } 319 320 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 321 fuTypeVec.map(fuType => 322 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 323 } 324 325 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 326 val mergeFuBusy = { 327 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 328 else canIssueVec.asUInt 329 } 330 val mergeIntWbBusy = { 331 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 332 else mergeFuBusy 333 } 334 val mergeVfWbBusy = { 335 if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i)) 336 else mergeIntWbBusy 337 } 338 merge := mergeVfWbBusy 339 } 340 341 deqCanIssue.zipWithIndex.foreach { case (req, i) => 342 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 343 } 344 dontTouch(fuTypeVec) 345 dontTouch(canIssueMergeAllBusy) 346 dontTouch(deqCanIssue) 347 348 if (params.numDeq == 2) { 349 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 350 } 351 352 if (params.numDeq == 2 && params.deqFuSame) { 353 val subDeqPolicy = Module(new DeqPolicy()) 354 355 enqEntryOldestSel := DontCare 356 357 if (params.isAllComp || params.isAllSimp) { 358 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 359 enq = othersEntryEnqSelVec.get, 360 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 361 ) 362 othersEntryOldestSel(1) := DontCare 363 364 subDeqPolicy.io.request := subDeqRequest.get 365 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 366 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 367 } 368 else { 369 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 370 simpAgeDetectRequest.get(1) := DontCare 371 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 372 if (params.numEnq == 2) { 373 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 374 } 375 376 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 377 enq = simpEntryEnqSelVec.get, 378 canIssue = simpAgeDetectRequest.get 379 ) 380 381 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 382 enq = compEntryEnqSelVec.get, 383 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 384 ) 385 compEntryOldestSel.get(1) := DontCare 386 387 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 388 othersEntryOldestSel(0).bits := Cat( 389 compEntryOldestSel.get(0).bits, 390 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 391 ) 392 othersEntryOldestSel(1) := DontCare 393 394 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 395 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 396 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 397 } 398 399 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 400 401 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 402 deqSelValidVec(1) := subDeqSelValidVec.get(0) 403 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 404 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 405 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 406 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 407 408 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 409 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 410 selOH := deqOH 411 } 412 } 413 else { 414 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 415 enq = VecInit(s0_doEnqSelValidVec), 416 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 417 ) 418 419 if (params.isAllComp || params.isAllSimp) { 420 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 421 enq = othersEntryEnqSelVec.get, 422 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 423 ) 424 425 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 426 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 427 selValid := false.B 428 selOH := 0.U.asTypeOf(selOH) 429 } else { 430 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 431 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 432 } 433 } 434 } 435 else { 436 othersEntryOldestSel := DontCare 437 438 deqCanIssue.zipWithIndex.foreach { case (req, i) => 439 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 440 } 441 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 442 if (params.numEnq == 2) { 443 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 444 } 445 446 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 447 enq = simpEntryEnqSelVec.get, 448 canIssue = simpAgeDetectRequest.get 449 ) 450 451 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 452 enq = compEntryEnqSelVec.get, 453 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 454 ) 455 456 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 457 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 458 selOH := Cat( 459 compEntryOldestSel.get(i).bits, 460 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 461 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 462 ) 463 } 464 } 465 466 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 467 selValid := deqValid && deqBeforeDly(i).ready 468 selOH := deqOH 469 } 470 } 471 472 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 473 474 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 475 deqResp.valid := finalDeqSelValidVec(i) 476 deqResp.bits.resp := RespType.success 477 deqResp.bits.robIdx := DontCare 478 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 479 deqResp.bits.uopIdx.foreach(_ := DontCare) 480 } 481 482 //fuBusyTable 483 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 484 if(busyTableWrite.nonEmpty) { 485 val btwr = busyTableWrite.get 486 val btrd = busyTableRead.get 487 btwr.io.in.deqResp := toBusyTableDeqResp(i) 488 btwr.io.in.og0Resp := io.og0Resp(i) 489 btwr.io.in.og1Resp := io.og1Resp(i) 490 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 491 btrd.io.in.fuTypeRegVec := fuTypeVec 492 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 493 } 494 else { 495 fuBusyTableMask(i) := 0.U(params.numEntries.W) 496 } 497 } 498 499 //wbfuBusyTable write 500 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 501 if(busyTableWrite.nonEmpty) { 502 val btwr = busyTableWrite.get 503 val bt = busyTable.get 504 val dq = deqResp.get 505 btwr.io.in.deqResp := toBusyTableDeqResp(i) 506 btwr.io.in.og0Resp := io.og0Resp(i) 507 btwr.io.in.og1Resp := io.og1Resp(i) 508 bt := btwr.io.out.fuBusyTable 509 dq := btwr.io.out.deqRespSet 510 } 511 } 512 513 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 514 if (busyTableWrite.nonEmpty) { 515 val btwr = busyTableWrite.get 516 val bt = busyTable.get 517 val dq = deqResp.get 518 btwr.io.in.deqResp := toBusyTableDeqResp(i) 519 btwr.io.in.og0Resp := io.og0Resp(i) 520 btwr.io.in.og1Resp := io.og1Resp(i) 521 bt := btwr.io.out.fuBusyTable 522 dq := btwr.io.out.deqRespSet 523 } 524 } 525 526 //wbfuBusyTable read 527 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 528 if(busyTableRead.nonEmpty) { 529 val btrd = busyTableRead.get 530 val bt = busyTable.get 531 btrd.io.in.fuBusyTable := bt 532 btrd.io.in.fuTypeRegVec := fuTypeVec 533 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 534 } 535 else { 536 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 537 } 538 } 539 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 540 if (busyTableRead.nonEmpty) { 541 val btrd = busyTableRead.get 542 val bt = busyTable.get 543 btrd.io.in.fuBusyTable := bt 544 btrd.io.in.fuTypeRegVec := fuTypeVec 545 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 546 } 547 else { 548 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 549 } 550 } 551 552 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 553 wakeUpQueueOption.foreach { 554 wakeUpQueue => 555 val flush = Wire(new WakeupQueueFlush) 556 flush.redirect := io.flush 557 flush.ldCancel := io.ldCancel 558 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 559 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 560 wakeUpQueue.io.flush := flush 561 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 562 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 563 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 564 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 565 } 566 } 567 568 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 569 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 570 deq.bits.addrOH := finalDeqSelOHVec(i) 571 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 572 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 573 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 574 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 575 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 576 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 577 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 578 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 579 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 580 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 581 582 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 583 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 584 deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i)) 585 deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i)) 586 deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i)) 587 deq.bits.common.src := DontCare 588 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 589 590 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 591 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 592 rf.foreach(_.addr := psrc) 593 rf.foreach(_.srcType := srcType) 594 } 595 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 596 sink := source 597 } 598 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 599 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 600 601 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 602 deq.bits.common.perfDebugInfo.selectTime := GTimer() 603 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 604 } 605 606 private val deqShift = WireDefault(deqBeforeDly) 607 deqShift.zip(deqBeforeDly).foreach { 608 case (shifted, original) => 609 original.ready := shifted.ready // this will not cause combinational loop 610 shifted.bits.common.loadDependency.foreach( 611 _ := original.bits.common.loadDependency.get.map(_ << 1) 612 ) 613 } 614 io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) => 615 NewPipelineConnect( 616 deq, deqDly, deqDly.valid, 617 false.B, 618 Option("Scheduler2DataPathPipe") 619 ) 620 } 621 if(backendParams.debugEn) { 622 dontTouch(io.deqDelay) 623 } 624 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 625 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 626 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 627 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 628 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 629 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 630 } else if (wakeUpQueues(i).nonEmpty) { 631 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 632 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 633 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 634 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 635 } else { 636 wakeup.valid := false.B 637 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 638 wakeup.bits.is0Lat := 0.U 639 } 640 if (wakeUpQueues(i).nonEmpty) { 641 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 642 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 643 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 644 } 645 646 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 647 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 648 } 649 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 650 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 651 } 652 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 653 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 654 } 655 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 656 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 657 } 658 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 659 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 660 } 661 } 662 663 // Todo: better counter implementation 664 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 665 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 666 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 667 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 668 for (i <- 0 until params.numEnq) { 669 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 670 } 671 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 672 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 673 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 674 } 675 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 676 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 677 678 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 679 io.status.empty := !Cat(validVec).orR 680 io.status.full := othersCanotIn 681 io.status.validCnt := PopCount(validVec) 682 683 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 684 Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 685 } 686 687 // issue perf counter 688 // enq count 689 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 690 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 691 // valid count 692 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 693 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 694 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 695 // only split when more than 1 func type 696 if (params.getFuCfgs.size > 0) { 697 for (t <- FuType.functionNameMap.keys) { 698 val fuName = FuType.functionNameMap(t) 699 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 700 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 701 } 702 } 703 } 704 // ready instr count 705 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 706 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 707 // only split when more than 1 func type 708 if (params.getFuCfgs.size > 0) { 709 for (t <- FuType.functionNameMap.keys) { 710 val fuName = FuType.functionNameMap(t) 711 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 712 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 713 } 714 } 715 } 716 717 // deq instr count 718 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 719 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 720 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 721 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 722 723 // deq instr data source count 724 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 725 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 726 }.reduce(_ +& _)) 727 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 728 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 729 }.reduce(_ +& _)) 730 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 731 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 732 }.reduce(_ +& _)) 733 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 734 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 735 }.reduce(_ +& _)) 736 737 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 738 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 739 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 740 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 741 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 742 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 743 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 744 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 745 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 746 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 747 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 748 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 749 750 // deq instr data source count for each futype 751 for (t <- FuType.functionNameMap.keys) { 752 val fuName = FuType.functionNameMap(t) 753 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 754 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 755 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 756 }.reduce(_ +& _)) 757 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 758 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 759 }.reduce(_ +& _)) 760 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 761 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 762 }.reduce(_ +& _)) 763 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 764 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 765 }.reduce(_ +& _)) 766 767 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 768 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 769 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 770 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 771 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 772 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 773 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 774 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 775 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 776 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 777 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 778 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 779 } 780 } 781 782 // cancel instr count 783 if (params.hasIQWakeUp) { 784 val cancelVec: Vec[Bool] = entries.io.cancel.get 785 XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2))) 786 XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1) 787 for (t <- FuType.functionNameMap.keys) { 788 val fuName = FuType.functionNameMap(t) 789 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 790 XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U })) 791 XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1) 792 } 793 } 794 } 795} 796 797class IssueQueueJumpBundle extends Bundle { 798 val pc = UInt(VAddrData().dataWidth.W) 799} 800 801class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 802 val fastMatch = UInt(backendParams.LduCnt.W) 803 val fastImm = UInt(12.W) 804} 805 806class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 807 808class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 809 extends IssueQueueImp(wrapper) 810{ 811 io.suggestName("none") 812 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 813 814 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 815 deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc) 816 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 817 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 818 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 819 deq.bits.common.predictInfo.foreach(x => { 820 x.target := DontCare 821 x.taken := deqEntryVec(i).bits.payload.pred_taken 822 }) 823 // for std 824 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 825 // for i2f 826 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 827 }} 828} 829 830class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 831 extends IssueQueueImp(wrapper) 832{ 833 s0_enqBits.foreach{ x => 834 x.srcType(3) := SrcType.vp // v0: mask src 835 x.srcType(4) := SrcType.vp // vl&vtype 836 } 837 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 838 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 839 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 840 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 841 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 842 }} 843} 844 845class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 846 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO)) 847 val checkWait = new Bundle { 848 val stIssuePtr = Input(new SqPtr) 849 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 850 } 851 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 852 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 853 854 // vector 855 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 856 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 857} 858 859class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 860 val memIO = Some(new IssueQueueMemBundle) 861} 862 863class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 864 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 865 866 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt + params.VlduCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 867 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 868 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 869 870 io.suggestName("none") 871 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 872 private val memIO = io.memIO.get 873 874 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 875 876 for (i <- io.enq.indices) { 877 val blockNotReleased = isAfter(io.enq(i).bits.sqIdx, memIO.checkWait.stIssuePtr) 878 val storeAddrWaitForIsIssuing = VecInit((0 until StorePipelineWidth).map(i => { 879 memIO.checkWait.memWaitUpdateReq.robIdx(i).valid && 880 memIO.checkWait.memWaitUpdateReq.robIdx(i).bits.value === io.enq(i).bits.waitForRobIdx.value 881 })).asUInt.orR && !io.enq(i).bits.loadWaitStrict // is waiting for store addr ready 882 s0_enqBits(i).loadWaitBit := io.enq(i).bits.loadWaitBit && !storeAddrWaitForIsIssuing && blockNotReleased 883 // when have vpu 884 if (params.VlduCnt > 0 || params.VstuCnt > 0) { 885 s0_enqBits(i).srcType(3) := SrcType.vp // v0: mask src 886 s0_enqBits(i).srcType(4) := SrcType.vp // vl&vtype 887 } 888 } 889 890 for (i <- entries.io.enq.indices) { 891 entries.io.enq(i).bits.status match { case enqData => 892 enqData.blocked := false.B // s0_enqBits(i).loadWaitBit 893 enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict 894 enqData.mem.get.waitForStd := false.B 895 enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx 896 enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later 897 enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx 898 } 899 } 900 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 901 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 902 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 903 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 904 slowResp.bits.fuType := DontCare 905 } 906 907 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 908 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 909 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 910 fastResp.bits.resp := RespType.block 911 fastResp.bits.fuType := DontCare 912 } 913 914 entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq 915 entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr 916 917 // load wakeup 918 val loadWakeUpIter = memIO.loadWakeUp.iterator 919 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 920 if (param.hasLoadExu) { 921 require(wakeUpQueues(i).isEmpty) 922 val uop = loadWakeUpIter.next() 923 924 wakeup.valid := RegNext(uop.fire) 925 wakeup.bits.rfWen := RegNext(uop.bits.rfWen && uop.fire) 926 wakeup.bits.fpWen := RegNext(uop.bits.fpWen && uop.fire) 927 wakeup.bits.vecWen := RegNext(uop.bits.vecWen && uop.fire) 928 wakeup.bits.pdest := RegNext(uop.bits.pdest) 929 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 930 931 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.rfWen && uop.fire))) 932 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.fpWen && uop.fire))) 933 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := RegNext(uop.bits.vecWen && uop.fire))) 934 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegNext(uop.bits.pdest))) 935 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 936 937 wakeup.bits.is0Lat := 0.U 938 } 939 } 940 require(!loadWakeUpIter.hasNext) 941 942 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 943 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 944 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 945 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 946 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 947 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 948 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 949 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 950 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 951 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 952 // when have vpu 953 if (params.VlduCnt > 0 || params.VstuCnt > 0) { 954 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 955 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 956 } 957 } 958} 959 960class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 961 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 962 963 require((params.VstdCnt + params.VlduCnt + params.VstaCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 964 965 io.suggestName("none") 966 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 967 private val memIO = io.memIO.get 968 969 def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = { 970 val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j)))) 971 val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j => 972 (if (j < i) !valid(j) || compareVec(i)(j) 973 else if (j == i) valid(i) 974 else !valid(j) || !compareVec(j)(i)) 975 )).andR)) 976 resultOnehot 977 } 978 979 val robIdxVec = entries.io.robIdx.get 980 val uopIdxVec = entries.io.uopIdx.get 981 val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec) 982 983 finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR 984 finalDeqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt 985 986 if (params.isVecMemAddrIQ) { 987 s0_enqBits.foreach{ x => 988 x.srcType(3) := SrcType.vp // v0: mask src 989 x.srcType(4) := SrcType.vp // vl&vtype 990 } 991 992 for (i <- io.enq.indices) { 993 s0_enqBits(i).loadWaitBit := false.B 994 } 995 996 for (i <- entries.io.enq.indices) { 997 entries.io.enq(i).bits.status match { case enqData => 998 enqData.blocked := false.B // s0_enqBits(i).loadWaitBit 999 enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict 1000 enqData.mem.get.waitForStd := false.B 1001 enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx 1002 enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later 1003 enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx 1004 } 1005 1006 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1007 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1008 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1009 slowResp.bits.resp := RespType.block 1010 slowResp.bits.fuType := DontCare 1011 } 1012 1013 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1014 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1015 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1016 fastResp.bits.resp := RespType.block 1017 fastResp.bits.fuType := DontCare 1018 } 1019 1020 entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq 1021 entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr 1022 } 1023 } 1024 1025 for (i <- entries.io.enq.indices) { 1026 entries.io.enq(i).bits.status.vecMem.get match { 1027 case enqData => 1028 enqData.sqIdx := s0_enqBits(i).sqIdx 1029 enqData.lqIdx := s0_enqBits(i).lqIdx 1030 enqData.uopIdx := s0_enqBits(i).uopIdx 1031 } 1032 } 1033 1034 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1035 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1036 1037 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (resp, i) => 1038 resp.bits.uopIdx.get := 0.U // Todo 1039 } 1040 1041 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (resp, i) => 1042 resp.bits.uopIdx.get := 0.U // Todo 1043 } 1044 1045 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1046 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 1047 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.payload.lqIdx) 1048 if (params.isVecLdAddrIQ) { 1049 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1050 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1051 } 1052 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1053 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1054 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1055 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1056 } 1057} 1058