1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne, XSPerfAccumulate, XSPerfHistogram} 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.issue.EntryBundles._ 11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 12import xiangshan.backend.datapath.DataConfig._ 13import xiangshan.backend.datapath.DataSource 14import xiangshan.backend.fu.{FuConfig, FuType} 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.rob.RobPtr 17import xiangshan.backend.datapath.NewPipelineConnect 18import xiangshan.backend.fu.vector.Bundles.VSew 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams: IssueBlockParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case FpScheduler() => new IssueQueueFpImp(this) 27 case VfScheduler() => new IssueQueueVfImp(this) 28 case MemScheduler() => 29 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 30 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 31 else new IssueQueueIntImp(this) 32 case _ => null 33 } 34} 35 36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 37 val empty = Output(Bool()) 38 val full = Output(Bool()) 39 val validCnt = Output(UInt(log2Ceil(numEntries + 1).W)) 40 val leftVec = Output(Vec(numEnq + 1, Bool())) 41} 42 43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 44 45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 46 // Inputs 47 val flush = Flipped(ValidIO(new Redirect)) 48 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 49 50 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val og2Resp = Option.when(params.needOg2Resp)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val finalIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val memAddrIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val vecLoadIssueResp = Option.when(params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle) 57 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle) 58 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 59 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 60 val vlIsZero = Input(Bool()) 61 val vlIsVlmax = Input(Bool()) 62 val og0Cancel = Input(ExuVec()) 63 val og1Cancel = Input(ExuVec()) 64 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 65 val replaceRCIdx = Option.when(params.needWriteRegCache)(Vec(params.numDeq, Input(UInt(RegCacheIdxWidth.W)))) 66 67 // Outputs 68 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 69 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 70 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 71 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 72 73 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 74 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 75} 76 77class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 78 extends LazyModuleImp(wrapper) 79 with HasXSParameter { 80 81 override def desiredName: String = s"${params.getIQName}" 82 83 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 84 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 85 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 86 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 87 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 88 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 89 90 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 91 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 92 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 93 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 94 95 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 96 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 97 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 98 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 99 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 100 101 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 102 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 103 lazy val io = IO(new IssueQueueIO()) 104 105 // Modules 106 val entries = Module(new Entries) 107 val fuBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableWrite(x.fuLatencyMap))) } 108 val fuBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableRead(x.fuLatencyMap))) } 109 val intWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 110 val intWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableRead(x.intFuLatencyMap))) } 111 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 112 val fpWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 113 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 114 val vfWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 115 val v0WbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableWrite(x.v0FuLatencyMap))) } 116 val v0WbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableRead(x.v0FuLatencyMap))) } 117 val vlWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableWrite(x.vlFuLatencyMap))) } 118 val vlWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableRead(x.vlFuLatencyMap))) } 119 120 class WakeupQueueFlush extends Bundle { 121 val redirect = ValidIO(new Redirect) 122 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 123 val og0Fail = Output(Bool()) 124 val og1Fail = Output(Bool()) 125 } 126 127 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 128 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 129 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 130 val ogFailFlush = stage match { 131 case 1 => flush.og0Fail 132 case 2 => flush.og1Fail 133 case _ => false.B 134 } 135 redirectFlush || loadDependencyFlush || ogFailFlush 136 } 137 138 private def modificationFunc(exuInput: ExuInput): ExuInput = { 139 val newExuInput = WireDefault(exuInput) 140 newExuInput.loadDependency match { 141 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 142 case None => 143 } 144 newExuInput 145 } 146 147 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 148 val lastExuInput = WireDefault(exuInput) 149 val newExuInput = WireDefault(newInput) 150 newExuInput.elements.foreach { case (name, data) => 151 if (lastExuInput.elements.contains(name)) { 152 data := lastExuInput.elements(name) 153 } 154 } 155 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 156 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 157 } 158 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 159 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 160 } 161 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 162 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 163 } 164 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 165 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get) 166 } 167 if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) { 168 newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get) 169 } 170 if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) { 171 newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get) 172 } 173 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 174 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 175 } 176 newExuInput 177 } 178 179 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => Option.when(x.isIQWakeUpSource && !x.hasLoadExu)(Module( 180 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 181 ))} 182 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 183 184 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 185 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 186 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 187 val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable) 188 val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable) 189 190 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 191 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 192 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 193 val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable) 194 val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable) 195 196 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 197 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 198 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 199 val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet) 200 val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet) 201 202 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 203 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 204 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 206 val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 207 val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 208 209 val s0_enqValidVec = io.enq.map(_.valid) 210 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 211 val s0_enqNotFlush = !io.flush.valid 212 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 213 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 214 215 216 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 217 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 218 219 val validVec = VecInit(entries.io.valid.asBools) 220 val issuedVec = VecInit(entries.io.issued.asBools) 221 val requestForTrans = VecInit(validVec.zip(issuedVec).map(x => x._1 && !x._2)) 222 val canIssueVec = VecInit(entries.io.canIssue.asBools) 223 dontTouch(canIssueVec) 224 val deqFirstIssueVec = entries.io.isFirstIssue 225 226 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 227 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 228 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 229 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 230 // (entryIdx)(srcIdx)(exuIdx) 231 val wakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = entries.io.srcWakeUpL1ExuOH 232 // (deqIdx)(srcIdx)(exuIdx) 233 val finalWakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 234 235 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 236 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 237 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 238 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 239 240 //deq 241 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 242 val simpEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 243 val compEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 244 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 245 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 246 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 247 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 248 249 val subDeqSelValidVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, Bool()))) 250 val subDeqSelOHVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 251 val subDeqRequest = Option.when(params.deqFuSame)(Wire(UInt(params.numEntries.W))) 252 253 //trans 254 val simpEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 255 val compEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 256 val othersEntryEnqSelVec = Option.when(params.isAllComp || params.isAllSimp)(Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 257 val simpAgeDetectRequest = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 258 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 259 260 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 261 // as vf exu's min latency is 1, we do not need consider og0cancel 262 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 263 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 264 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 265 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 266 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 267 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 268 } else { 269 w := w_src 270 } 271 } 272 273 /** 274 * Connection of [[entries]] 275 */ 276 entries.io match { case entriesIO: EntriesIO => 277 entriesIO.flush := io.flush 278 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 279 enq.valid := s0_doEnqSelValidVec(enqIdx) 280 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 281 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 282 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 283 for(j <- 0 until numLsrc) { 284 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 285 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 286 enq.bits.status.srcStatus(j).srcState := (if (j < 3) { 287 Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 288 SrcState.rdy, 289 s0_enqBits(enqIdx).srcState(j)) 290 } else { 291 s0_enqBits(enqIdx).srcState(j) 292 }) 293 enq.bits.status.srcStatus(j).dataSources.value := (if (j < 3) { 294 MuxCase(DataSource.reg, Seq( 295 (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero, 296 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 297 (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0, 298 )) 299 } else { 300 MuxCase(DataSource.reg, Seq( 301 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 302 )) 303 }) 304 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 305 if(params.hasIQWakeUp) { 306 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 307 } 308 enq.bits.status.srcStatus(j).useRegCache.foreach(_ := s0_enqBits(enqIdx).useRegCache(j)) 309 enq.bits.status.srcStatus(j).regCacheIdx.foreach(_ := s0_enqBits(enqIdx).regCacheIdx(j)) 310 } 311 enq.bits.status.blocked := false.B 312 enq.bits.status.issued := false.B 313 enq.bits.status.firstIssue := false.B 314 enq.bits.status.issueTimer := "b11".U 315 enq.bits.status.deqPortIdx := 0.U 316 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 317 enq.bits.payload := s0_enqBits(enqIdx) 318 } 319 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 320 og0Resp := io.og0Resp(i) 321 } 322 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 323 og1Resp := io.og1Resp(i) 324 } 325 if (params.needOg2Resp) { 326 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 327 og2Resp := io.og2Resp.get(i) 328 } 329 } 330 if (params.isLdAddrIQ || params.isHyAddrIQ) { 331 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 332 finalIssueResp := io.finalIssueResp.get(i) 333 } 334 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 335 memAddrIssueResp := io.memAddrIssueResp.get(i) 336 } 337 } 338 if (params.isVecLduIQ) { 339 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 340 resp := io.vecLoadIssueResp.get(i) 341 } 342 } 343 for(deqIdx <- 0 until params.numDeq) { 344 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 345 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 346 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 347 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 348 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 349 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 350 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 351 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 352 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 353 } 354 entriesIO.wakeUpFromWB := io.wakeupFromWB 355 entriesIO.wakeUpFromIQ := wakeupFromIQ 356 entriesIO.vlIsZero := io.vlIsZero 357 entriesIO.vlIsVlmax := io.vlIsVlmax 358 entriesIO.og0Cancel := io.og0Cancel 359 entriesIO.og1Cancel := io.og1Cancel 360 entriesIO.ldCancel := io.ldCancel 361 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 362 //output 363 fuTypeVec := entriesIO.fuType 364 deqEntryVec := entriesIO.deqEntry 365 cancelDeqVec := entriesIO.cancelDeqVec 366 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 367 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 368 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 369 } 370 371 372 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 373 374 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 375 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 376 ).reverse) 377 378 // if deq port can accept the uop 379 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 380 Cat(fuTypeVec.map(fuType => 381 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 382 ).reverse) 383 } 384 385 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 386 fuTypeVec.map(fuType => 387 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 388 } 389 390 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 391 val mergeFuBusy = { 392 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 393 else canIssueVec.asUInt 394 } 395 val mergeIntWbBusy = { 396 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 397 else mergeFuBusy 398 } 399 val mergefpWbBusy = { 400 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 401 else mergeIntWbBusy 402 } 403 val mergeVfWbBusy = { 404 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 405 else mergefpWbBusy 406 } 407 val mergeV0WbBusy = { 408 if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i)) 409 else mergeVfWbBusy 410 } 411 val mergeVlWbBusy = { 412 if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i)) 413 else mergeV0WbBusy 414 } 415 merge := mergeVlWbBusy 416 } 417 418 deqCanIssue.zipWithIndex.foreach { case (req, i) => 419 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 420 } 421 dontTouch(fuTypeVec) 422 dontTouch(canIssueMergeAllBusy) 423 dontTouch(deqCanIssue) 424 425 if (params.numDeq == 2) { 426 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 427 } 428 429 if (params.numDeq == 2 && params.deqFuSame) { 430 val subDeqPolicy = Module(new DeqPolicy()) 431 432 enqEntryOldestSel := DontCare 433 434 if (params.isAllComp || params.isAllSimp) { 435 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 436 enq = othersEntryEnqSelVec.get, 437 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 438 ) 439 othersEntryOldestSel(1) := DontCare 440 441 subDeqPolicy.io.request := subDeqRequest.get 442 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 443 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 444 } 445 else { 446 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 447 simpAgeDetectRequest.get(1) := DontCare 448 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 449 if (params.numEnq == 2) { 450 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 451 } 452 453 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 454 enq = simpEntryEnqSelVec.get, 455 canIssue = simpAgeDetectRequest.get 456 ) 457 458 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 459 enq = compEntryEnqSelVec.get, 460 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 461 ) 462 compEntryOldestSel.get(1) := DontCare 463 464 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 465 othersEntryOldestSel(0).bits := Cat( 466 compEntryOldestSel.get(0).bits, 467 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 468 ) 469 othersEntryOldestSel(1) := DontCare 470 471 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 472 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 473 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 474 } 475 476 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 477 478 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 479 deqSelValidVec(1) := subDeqSelValidVec.get(0) 480 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 481 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 482 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 483 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 484 485 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 486 selValid := deqValid && deqOH.orR 487 selOH := deqOH 488 } 489 } 490 else { 491 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 492 enq = VecInit(s0_doEnqSelValidVec), 493 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 494 ) 495 496 if (params.isAllComp || params.isAllSimp) { 497 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 498 enq = othersEntryEnqSelVec.get, 499 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 500 ) 501 502 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 503 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 504 selValid := false.B 505 selOH := 0.U.asTypeOf(selOH) 506 } else { 507 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 508 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 509 } 510 } 511 } 512 else { 513 othersEntryOldestSel := DontCare 514 515 deqCanIssue.zipWithIndex.foreach { case (req, i) => 516 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 517 } 518 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 519 if (params.numEnq == 2) { 520 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 521 } 522 523 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 524 enq = simpEntryEnqSelVec.get, 525 canIssue = simpAgeDetectRequest.get 526 ) 527 528 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 529 enq = compEntryEnqSelVec.get, 530 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 531 ) 532 533 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 534 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 535 selValid := false.B 536 selOH := 0.U.asTypeOf(selOH) 537 } else { 538 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 539 selOH := Cat( 540 compEntryOldestSel.get(i).bits, 541 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 542 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 543 ) 544 } 545 } 546 } 547 548 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 549 selValid := deqValid 550 selOH := deqOH 551 } 552 } 553 554 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 555 556 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 557 deqResp.valid := deqBeforeDly(i).valid 558 deqResp.bits.resp := RespType.success 559 deqResp.bits.robIdx := DontCare 560 deqResp.bits.sqIdx.foreach(_ := DontCare) 561 deqResp.bits.lqIdx.foreach(_ := DontCare) 562 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 563 deqResp.bits.uopIdx.foreach(_ := DontCare) 564 } 565 566 //fuBusyTable 567 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 568 if(busyTableWrite.nonEmpty) { 569 val btwr = busyTableWrite.get 570 val btrd = busyTableRead.get 571 btwr.io.in.deqResp := toBusyTableDeqResp(i) 572 btwr.io.in.og0Resp := io.og0Resp(i) 573 btwr.io.in.og1Resp := io.og1Resp(i) 574 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 575 btrd.io.in.fuTypeRegVec := fuTypeVec 576 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 577 } 578 else { 579 fuBusyTableMask(i) := 0.U(params.numEntries.W) 580 } 581 } 582 583 //wbfuBusyTable write 584 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 585 if(busyTableWrite.nonEmpty) { 586 val btwr = busyTableWrite.get 587 val bt = busyTable.get 588 val dq = deqResp.get 589 btwr.io.in.deqResp := toBusyTableDeqResp(i) 590 btwr.io.in.og0Resp := io.og0Resp(i) 591 btwr.io.in.og1Resp := io.og1Resp(i) 592 bt := btwr.io.out.fuBusyTable 593 dq := btwr.io.out.deqRespSet 594 } 595 } 596 597 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 598 if (busyTableWrite.nonEmpty) { 599 val btwr = busyTableWrite.get 600 val bt = busyTable.get 601 val dq = deqResp.get 602 btwr.io.in.deqResp := toBusyTableDeqResp(i) 603 btwr.io.in.og0Resp := io.og0Resp(i) 604 btwr.io.in.og1Resp := io.og1Resp(i) 605 bt := btwr.io.out.fuBusyTable 606 dq := btwr.io.out.deqRespSet 607 } 608 } 609 610 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 611 if (busyTableWrite.nonEmpty) { 612 val btwr = busyTableWrite.get 613 val bt = busyTable.get 614 val dq = deqResp.get 615 btwr.io.in.deqResp := toBusyTableDeqResp(i) 616 btwr.io.in.og0Resp := io.og0Resp(i) 617 btwr.io.in.og1Resp := io.og1Resp(i) 618 bt := btwr.io.out.fuBusyTable 619 dq := btwr.io.out.deqRespSet 620 } 621 } 622 623 v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 624 if (busyTableWrite.nonEmpty) { 625 val btwr = busyTableWrite.get 626 val bt = busyTable.get 627 val dq = deqResp.get 628 btwr.io.in.deqResp := toBusyTableDeqResp(i) 629 btwr.io.in.og0Resp := io.og0Resp(i) 630 btwr.io.in.og1Resp := io.og1Resp(i) 631 bt := btwr.io.out.fuBusyTable 632 dq := btwr.io.out.deqRespSet 633 } 634 } 635 636 vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 637 if (busyTableWrite.nonEmpty) { 638 val btwr = busyTableWrite.get 639 val bt = busyTable.get 640 val dq = deqResp.get 641 btwr.io.in.deqResp := toBusyTableDeqResp(i) 642 btwr.io.in.og0Resp := io.og0Resp(i) 643 btwr.io.in.og1Resp := io.og1Resp(i) 644 bt := btwr.io.out.fuBusyTable 645 dq := btwr.io.out.deqRespSet 646 } 647 } 648 649 //wbfuBusyTable read 650 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 651 if(busyTableRead.nonEmpty) { 652 val btrd = busyTableRead.get 653 val bt = busyTable.get 654 btrd.io.in.fuBusyTable := bt 655 btrd.io.in.fuTypeRegVec := fuTypeVec 656 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 657 } 658 else { 659 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 660 } 661 } 662 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 663 if (busyTableRead.nonEmpty) { 664 val btrd = busyTableRead.get 665 val bt = busyTable.get 666 btrd.io.in.fuBusyTable := bt 667 btrd.io.in.fuTypeRegVec := fuTypeVec 668 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 669 } 670 else { 671 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 672 } 673 } 674 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 675 if (busyTableRead.nonEmpty) { 676 val btrd = busyTableRead.get 677 val bt = busyTable.get 678 btrd.io.in.fuBusyTable := bt 679 btrd.io.in.fuTypeRegVec := fuTypeVec 680 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 681 } 682 else { 683 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 684 } 685 } 686 v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 687 if (busyTableRead.nonEmpty) { 688 val btrd = busyTableRead.get 689 val bt = busyTable.get 690 btrd.io.in.fuBusyTable := bt 691 btrd.io.in.fuTypeRegVec := fuTypeVec 692 v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 693 } 694 else { 695 v0WbBusyTableMask(i) := 0.U(params.numEntries.W) 696 } 697 } 698 vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 699 if (busyTableRead.nonEmpty) { 700 val btrd = busyTableRead.get 701 val bt = busyTable.get 702 btrd.io.in.fuBusyTable := bt 703 btrd.io.in.fuTypeRegVec := fuTypeVec 704 vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 705 } 706 else { 707 vlWbBusyTableMask(i) := 0.U(params.numEntries.W) 708 } 709 } 710 711 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 712 wakeUpQueueOption.foreach { 713 wakeUpQueue => 714 val flush = Wire(new WakeupQueueFlush) 715 flush.redirect := io.flush 716 flush.ldCancel := io.ldCancel 717 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 718 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 719 wakeUpQueue.io.flush := flush 720 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 721 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 722 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 723 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 724 } 725 } 726 727 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 728 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 729 deq.bits.addrOH := finalDeqSelOHVec(i) 730 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 731 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 732 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 733 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 734 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 735 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 736 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 737 deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen) 738 deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen) 739 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 740 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 741 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 742 743 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 744 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 745 deq.bits.common.l1ExuOH.foreach(_.zip(finalWakeUpL1ExuOH.get(i)).foreach { case (sink, source) => sink := source}) 746 deq.bits.common.srcTimer.foreach(_ := DontCare) 747 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 748 deq.bits.common.src := DontCare 749 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 750 751 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 752 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 753 rf.foreach(_.addr := psrc) 754 rf.foreach(_.srcType := srcType) 755 } 756 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 757 sink := source 758 } 759 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 760 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 761 deq.bits.rcIdx.foreach(_ := deqEntryVec(i).bits.status.srcStatus.map(_.regCacheIdx.get)) 762 763 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 764 deq.bits.common.perfDebugInfo.selectTime := GTimer() 765 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 766 } 767 768 io.deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 769 deqDly.valid := RegNext(deq.valid) 770 deqDly.bits := RegNext(deq.bits) 771 deq.ready := true.B 772 } 773 if(backendParams.debugEn) { 774 dontTouch(io.deqDelay) 775 dontTouch(deqBeforeDly) 776 } 777 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 778 if (wakeUpQueues(i).nonEmpty) { 779 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 780 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 781 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 782 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 783 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 784 } else { 785 wakeup.valid := false.B 786 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 787 } 788 if (wakeUpQueues(i).nonEmpty) { 789 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 790 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 791 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 792 wakeup.bits.v0Wen := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B) 793 wakeup.bits.vlWen := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B) 794 } 795 796 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 797 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 798 } 799 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 800 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 801 } 802 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 803 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 804 } 805 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 806 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 807 } 808 if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) { 809 wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get 810 } 811 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) { 812 wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get 813 } 814 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 815 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 816 } 817 } 818 819 // Todo: better counter implementation 820 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 821 private val enqHasIssued = validVec.zip(issuedVec).take(params.numEnq).map(x => x._1 & x._2).reduce(_ | _) 822 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 823 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 824 private val enqEntryValidCntDeq0 = PopCount( 825 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 826 ) 827 private val othersValidCntDeq0 = PopCount( 828 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 829 ) 830 private val enqEntryValidCntDeq1 = PopCount( 831 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 832 ) 833 private val othersValidCntDeq1 = PopCount( 834 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 835 ) 836 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 837 io.enq.map(_.bits.fuType).map(fuType => 838 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 839 } 840 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 841 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 842 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 843 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 844 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 845 for (i <- 0 until params.numEnq) { 846 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 847 } 848 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 849 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 850 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 851 } 852 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 853 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 854 855 io.enq.foreach(_.ready := (!othersCanotIn || !enqHasValid) && !enqHasIssued) 856 io.status.empty := !Cat(validVec).orR 857 io.status.full := othersCanotIn 858 io.status.validCnt := PopCount(validVec) 859 860 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 861 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 862 } 863 864 // issue perf counter 865 // enq count 866 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 867 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 868 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 869 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 870 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 871 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 872 // valid count 873 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 874 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 875 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 876 // only split when more than 1 func type 877 if (params.getFuCfgs.size > 0) { 878 for (t <- FuType.functionNameMap.keys) { 879 val fuName = FuType.functionNameMap(t) 880 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 881 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 882 } 883 } 884 } 885 // ready instr count 886 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 887 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 888 // only split when more than 1 func type 889 if (params.getFuCfgs.size > 0) { 890 for (t <- FuType.functionNameMap.keys) { 891 val fuName = FuType.functionNameMap(t) 892 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 893 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 894 } 895 } 896 } 897 898 // deq instr count 899 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 900 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 901 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 902 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 903 904 // deq instr data source count 905 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 906 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 907 }.reduce(_ +& _)) 908 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 909 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 910 }.reduce(_ +& _)) 911 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 912 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 913 }.reduce(_ +& _)) 914 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 915 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 916 }.reduce(_ +& _)) 917 918 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 919 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 920 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 921 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 922 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 923 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 924 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 925 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 926 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 927 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 928 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 929 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 930 931 // deq instr data source count for each futype 932 for (t <- FuType.functionNameMap.keys) { 933 val fuName = FuType.functionNameMap(t) 934 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 935 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 936 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 937 }.reduce(_ +& _)) 938 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 939 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 940 }.reduce(_ +& _)) 941 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 942 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 943 }.reduce(_ +& _)) 944 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 945 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 946 }.reduce(_ +& _)) 947 948 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 949 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 950 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 951 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 952 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 953 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 954 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 955 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 956 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 957 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 958 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 959 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 960 } 961 } 962} 963 964class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 965 val fastMatch = UInt(backendParams.LduCnt.W) 966 val fastImm = UInt(12.W) 967} 968 969class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 970 971class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 972 extends IssueQueueImp(wrapper) 973{ 974 io.suggestName("none") 975 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 976 977 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 978 deq.bits.common.pc.foreach(_ := DontCare) 979 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 980 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 981 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 982 deq.bits.common.predictInfo.foreach(x => { 983 x.target := DontCare 984 x.taken := deqEntryVec(i).bits.payload.pred_taken 985 }) 986 // for std 987 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 988 // for i2f 989 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 990 }} 991} 992 993class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 994 extends IssueQueueImp(wrapper) 995{ 996 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 997 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 998 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 999 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1000 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1001 }} 1002} 1003 1004class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1005 extends IssueQueueImp(wrapper) 1006{ 1007 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1008 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1009 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1010 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1011 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1012 }} 1013} 1014 1015class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 1016 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 1017 1018 // TODO: is still needed? 1019 val checkWait = new Bundle { 1020 val stIssuePtr = Input(new SqPtr) 1021 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 1022 } 1023 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 1024 1025 // load wakeup 1026 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 1027 1028 // vector 1029 val sqDeqPtr = Option.when(params.isVecMemIQ)(Input(new SqPtr)) 1030 val lqDeqPtr = Option.when(params.isVecMemIQ)(Input(new LqPtr)) 1031} 1032 1033class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 1034 val memIO = Some(new IssueQueueMemBundle) 1035} 1036 1037class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1038 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1039 1040 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 1041 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1042 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1043 1044 io.suggestName("none") 1045 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1046 private val memIO = io.memIO.get 1047 1048 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 1049 1050 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1051 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1052 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1053 slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx) 1054 slowResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx) 1055 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1056 slowResp.bits.fuType := DontCare 1057 } 1058 1059 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1060 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1061 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1062 fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx) 1063 fastResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.lqIdx) 1064 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1065 fastResp.bits.fuType := DontCare 1066 } 1067 1068 // load wakeup 1069 val loadWakeUpIter = memIO.loadWakeUp.iterator 1070 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 1071 if (param.hasLoadExu) { 1072 require(wakeUpQueues(i).isEmpty) 1073 val uop = loadWakeUpIter.next() 1074 1075 wakeup.valid := GatedValidRegNext(uop.fire) 1076 wakeup.bits.rfWen := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B) 1077 wakeup.bits.fpWen := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B) 1078 wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B) 1079 wakeup.bits.v0Wen := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B) 1080 wakeup.bits.vlWen := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B) 1081 wakeup.bits.pdest := RegNext(uop.bits.pdest) 1082 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 1083 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 1084 1085 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B))) 1086 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B))) 1087 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B))) 1088 wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B))) 1089 wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B))) 1090 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegNext(uop.bits.pdest))) 1091 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 1092 1093 wakeup.bits.is0Lat := 0.U 1094 } 1095 } 1096 require(!loadWakeUpIter.hasNext) 1097 1098 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1099 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 1100 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 1101 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 1102 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 1103 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 1104 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 1105 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 1106 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1107 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1108 } 1109} 1110 1111class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1112 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1113 1114 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1115 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1116 1117 io.suggestName("none") 1118 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1119 private val memIO = io.memIO.get 1120 1121 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1122 1123 for (i <- entries.io.enq.indices) { 1124 entries.io.enq(i).bits.status match { case enqData => 1125 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1126 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1127 // MemAddrIQ also handle vector insts 1128 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1129 enqData.blocked := false.B 1130 } 1131 } 1132 1133 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1134 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1135 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1136 slowResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx 1137 slowResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx 1138 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1139 slowResp.bits.fuType := DontCare 1140 slowResp.bits.uopIdx.get := DontCare 1141 } 1142 1143 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1144 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1145 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1146 fastResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.sqIdx 1147 fastResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.lqIdx 1148 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1149 fastResp.bits.fuType := DontCare 1150 fastResp.bits.uopIdx.get := DontCare 1151 } 1152 1153 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1154 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1155 1156 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1157 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1158 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1159 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1160 if (params.isVecLduIQ) { 1161 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1162 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1163 } 1164 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1165 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1166 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1167 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1168 } 1169 1170 io.vecLoadIssueResp.foreach(dontTouch(_)) 1171} 1172