1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case VfScheduler() => new IssueQueueVfImp(this) 27 case MemScheduler() => 28 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 29 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 30 else new IssueQueueIntImp(this) 31 case _ => null 32 } 33} 34 35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 36 val empty = Output(Bool()) 37 val full = Output(Bool()) 38 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 39 val leftVec = Output(Vec(numEnq + 1, Bool())) 40} 41 42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 43 44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 45 // Inputs 46 val flush = Flipped(ValidIO(new Redirect)) 47 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 48 49 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 50 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 52 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 54 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 55 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 56 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 57 val og0Cancel = Input(ExuOH(backendParams.numExu)) 58 val og1Cancel = Input(ExuOH(backendParams.numExu)) 59 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 60 61 // Outputs 62 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 63 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 64 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 65 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 66 67 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 68 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 69} 70 71class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 72 extends LazyModuleImp(wrapper) 73 with HasXSParameter { 74 75 override def desiredName: String = s"${params.getIQName}" 76 77 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 78 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 79 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 80 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 81 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 82 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 83 84 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 85 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 86 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 87 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 88 89 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 90 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 91 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 92 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 93 val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap) 94 95 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}") 96 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 97 lazy val io = IO(new IssueQueueIO()) 98 99 // Modules 100 val entries = Module(new Entries) 101 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 102 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 103 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 104 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 105 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 106 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 107 108 class WakeupQueueFlush extends Bundle { 109 val redirect = ValidIO(new Redirect) 110 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 111 val og0Fail = Output(Bool()) 112 val og1Fail = Output(Bool()) 113 } 114 115 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 116 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 117 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 118 val ogFailFlush = stage match { 119 case 1 => flush.og0Fail 120 case 2 => flush.og1Fail 121 case _ => false.B 122 } 123 redirectFlush || loadDependencyFlush || ogFailFlush 124 } 125 126 private def modificationFunc(exuInput: ExuInput): ExuInput = { 127 val newExuInput = WireDefault(exuInput) 128 newExuInput.loadDependency match { 129 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 130 case None => 131 } 132 newExuInput 133 } 134 135 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 136 val lastExuInput = WireDefault(exuInput) 137 val newExuInput = WireDefault(newInput) 138 newExuInput.elements.foreach { case (name, data) => 139 if (lastExuInput.elements.contains(name)) { 140 data := lastExuInput.elements(name) 141 } 142 } 143 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 144 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 145 } 146 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 147 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 148 } 149 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 150 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 151 } 152 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 153 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 154 } 155 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 156 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 157 } 158 newExuInput 159 } 160 161 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 162 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 163 ))} 164 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 165 166 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 167 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 168 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 169 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 170 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 171 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 172 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 173 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 174 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 175 val s0_enqValidVec = io.enq.map(_.valid) 176 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 177 val s0_enqNotFlush = !io.flush.valid 178 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 179 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 180 181 182 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 183 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 184 185 val validVec = VecInit(entries.io.valid.asBools) 186 val canIssueVec = VecInit(entries.io.canIssue.asBools) 187 dontTouch(canIssueVec) 188 val deqFirstIssueVec = entries.io.isFirstIssue 189 190 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 191 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 192 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 193 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 194 // (entryIdx)(srcIdx)(exuIdx) 195 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 196 val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer 197 198 // (deqIdx)(srcIdx)(exuIdx) 199 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 200 val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 201 202 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 203 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 204 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 206 207 //deq 208 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 209 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 210 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 211 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 212 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 213 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 214 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 215 216 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 217 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 218 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 219 220 //trans 221 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 222 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 223 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 224 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 225 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 226 227 /** 228 * Connection of [[entries]] 229 */ 230 entries.io match { case entriesIO: EntriesIO => 231 entriesIO.flush := io.flush 232 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 233 enq.valid := s0_doEnqSelValidVec(enqIdx) 234 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 235 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 236 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 237 for(j <- 0 until numLsrc) { 238 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 239 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 240 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 241 enq.bits.status.srcStatus(j).dataSources.value := Mux( 242 SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 243 DataSource.zero, 244 Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg) 245 ) 246 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1)) 247 if(params.hasIQWakeUp) { 248 enq.bits.status.srcStatus(j).srcTimer.get := 0.U(3.W) 249 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 250 } 251 } 252 enq.bits.status.blocked := false.B 253 enq.bits.status.issued := false.B 254 enq.bits.status.firstIssue := false.B 255 enq.bits.status.issueTimer := "b10".U 256 enq.bits.status.deqPortIdx := 0.U 257 if (params.inIntSchd && params.AluCnt > 0) { 258 // dirty code for lui+addi(w) fusion 259 val isLuiAddiFusion = s0_enqBits(enqIdx).isLUI32 260 val luiImm = Cat(s0_enqBits(enqIdx).lsrc(1), s0_enqBits(enqIdx).lsrc(0), s0_enqBits(enqIdx).imm(ImmUnion.maxLen - 1, 0)) 261 enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(enqIdx).imm)) 262 } 263 else if (params.isLdAddrIQ || params.isHyAddrIQ) { 264 // dirty code for fused_lui_load 265 val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(enqIdx).srcType(0)) && FuType.isLoad(s0_enqBits(enqIdx).fuType) 266 enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(enqIdx)), s0_enqBits(enqIdx).imm)) 267 } 268 else { 269 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 270 } 271 enq.bits.payload := s0_enqBits(enqIdx) 272 } 273 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 274 og0Resp := io.og0Resp(i) 275 } 276 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 277 og1Resp := io.og1Resp(i) 278 } 279 if (params.isLdAddrIQ || params.isHyAddrIQ) { 280 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 281 finalIssueResp := io.finalIssueResp.get(i) 282 } 283 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 284 memAddrIssueResp := io.memAddrIssueResp.get(i) 285 } 286 } 287 for(deqIdx <- 0 until params.numDeq) { 288 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 289 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 290 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 291 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 292 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 293 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 294 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 295 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 296 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 297 } 298 entriesIO.wakeUpFromWB := io.wakeupFromWB 299 entriesIO.wakeUpFromIQ := io.wakeupFromIQ 300 entriesIO.og0Cancel := io.og0Cancel 301 entriesIO.og1Cancel := io.og1Cancel 302 entriesIO.ldCancel := io.ldCancel 303 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 304 //output 305 fuTypeVec := entriesIO.fuType 306 deqEntryVec := entriesIO.deqEntry 307 cancelDeqVec := entriesIO.cancelDeqVec 308 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 309 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 310 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 311 } 312 313 314 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 315 316 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 317 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 318 ).reverse) 319 320 // if deq port can accept the uop 321 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 322 Cat(fuTypeVec.map(fuType => 323 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 324 ).reverse) 325 } 326 327 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 328 fuTypeVec.map(fuType => 329 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 330 } 331 332 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 333 val mergeFuBusy = { 334 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 335 else canIssueVec.asUInt 336 } 337 val mergeIntWbBusy = { 338 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 339 else mergeFuBusy 340 } 341 val mergeVfWbBusy = { 342 if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i)) 343 else mergeIntWbBusy 344 } 345 merge := mergeVfWbBusy 346 } 347 348 deqCanIssue.zipWithIndex.foreach { case (req, i) => 349 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 350 } 351 dontTouch(fuTypeVec) 352 dontTouch(canIssueMergeAllBusy) 353 dontTouch(deqCanIssue) 354 355 if (params.numDeq == 2) { 356 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 357 } 358 359 if (params.numDeq == 2 && params.deqFuSame) { 360 val subDeqPolicy = Module(new DeqPolicy()) 361 362 enqEntryOldestSel := DontCare 363 364 if (params.isAllComp || params.isAllSimp) { 365 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 366 enq = othersEntryEnqSelVec.get, 367 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 368 ) 369 othersEntryOldestSel(1) := DontCare 370 371 subDeqPolicy.io.request := subDeqRequest.get 372 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 373 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 374 } 375 else { 376 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 377 simpAgeDetectRequest.get(1) := DontCare 378 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 379 if (params.numEnq == 2) { 380 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 381 } 382 383 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 384 enq = simpEntryEnqSelVec.get, 385 canIssue = simpAgeDetectRequest.get 386 ) 387 388 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 389 enq = compEntryEnqSelVec.get, 390 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 391 ) 392 compEntryOldestSel.get(1) := DontCare 393 394 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 395 othersEntryOldestSel(0).bits := Cat( 396 compEntryOldestSel.get(0).bits, 397 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 398 ) 399 othersEntryOldestSel(1) := DontCare 400 401 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 402 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 403 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 404 } 405 406 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 407 408 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 409 deqSelValidVec(1) := subDeqSelValidVec.get(0) 410 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 411 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 412 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 413 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 414 415 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 416 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 417 selOH := deqOH 418 } 419 } 420 else { 421 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 422 enq = VecInit(s0_doEnqSelValidVec), 423 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 424 ) 425 426 if (params.isAllComp || params.isAllSimp) { 427 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 428 enq = othersEntryEnqSelVec.get, 429 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 430 ) 431 432 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 433 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 434 selValid := false.B 435 selOH := 0.U.asTypeOf(selOH) 436 } else { 437 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 438 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 439 } 440 } 441 } 442 else { 443 othersEntryOldestSel := DontCare 444 445 deqCanIssue.zipWithIndex.foreach { case (req, i) => 446 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 447 } 448 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 449 if (params.numEnq == 2) { 450 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 451 } 452 453 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 454 enq = simpEntryEnqSelVec.get, 455 canIssue = simpAgeDetectRequest.get 456 ) 457 458 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 459 enq = compEntryEnqSelVec.get, 460 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 461 ) 462 463 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 464 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 465 selValid := false.B 466 selOH := 0.U.asTypeOf(selOH) 467 } else { 468 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 469 selOH := Cat( 470 compEntryOldestSel.get(i).bits, 471 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 472 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 473 ) 474 } 475 } 476 } 477 478 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 479 selValid := deqValid && deqBeforeDly(i).ready 480 selOH := deqOH 481 } 482 } 483 484 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 485 486 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 487 deqResp.valid := finalDeqSelValidVec(i) 488 deqResp.bits.resp := RespType.success 489 deqResp.bits.robIdx := DontCare 490 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 491 deqResp.bits.uopIdx.foreach(_ := DontCare) 492 } 493 494 //fuBusyTable 495 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 496 if(busyTableWrite.nonEmpty) { 497 val btwr = busyTableWrite.get 498 val btrd = busyTableRead.get 499 btwr.io.in.deqResp := toBusyTableDeqResp(i) 500 btwr.io.in.og0Resp := io.og0Resp(i) 501 btwr.io.in.og1Resp := io.og1Resp(i) 502 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 503 btrd.io.in.fuTypeRegVec := fuTypeVec 504 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 505 } 506 else { 507 fuBusyTableMask(i) := 0.U(params.numEntries.W) 508 } 509 } 510 511 //wbfuBusyTable write 512 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 513 if(busyTableWrite.nonEmpty) { 514 val btwr = busyTableWrite.get 515 val bt = busyTable.get 516 val dq = deqResp.get 517 btwr.io.in.deqResp := toBusyTableDeqResp(i) 518 btwr.io.in.og0Resp := io.og0Resp(i) 519 btwr.io.in.og1Resp := io.og1Resp(i) 520 bt := btwr.io.out.fuBusyTable 521 dq := btwr.io.out.deqRespSet 522 } 523 } 524 525 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 526 if (busyTableWrite.nonEmpty) { 527 val btwr = busyTableWrite.get 528 val bt = busyTable.get 529 val dq = deqResp.get 530 btwr.io.in.deqResp := toBusyTableDeqResp(i) 531 btwr.io.in.og0Resp := io.og0Resp(i) 532 btwr.io.in.og1Resp := io.og1Resp(i) 533 bt := btwr.io.out.fuBusyTable 534 dq := btwr.io.out.deqRespSet 535 } 536 } 537 538 //wbfuBusyTable read 539 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 540 if(busyTableRead.nonEmpty) { 541 val btrd = busyTableRead.get 542 val bt = busyTable.get 543 btrd.io.in.fuBusyTable := bt 544 btrd.io.in.fuTypeRegVec := fuTypeVec 545 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 546 } 547 else { 548 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 549 } 550 } 551 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 552 if (busyTableRead.nonEmpty) { 553 val btrd = busyTableRead.get 554 val bt = busyTable.get 555 btrd.io.in.fuBusyTable := bt 556 btrd.io.in.fuTypeRegVec := fuTypeVec 557 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 558 } 559 else { 560 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 561 } 562 } 563 564 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 565 wakeUpQueueOption.foreach { 566 wakeUpQueue => 567 val flush = Wire(new WakeupQueueFlush) 568 flush.redirect := io.flush 569 flush.ldCancel := io.ldCancel 570 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 571 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 572 wakeUpQueue.io.flush := flush 573 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 574 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 575 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 576 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 577 } 578 } 579 580 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 581 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 582 deq.bits.addrOH := finalDeqSelOHVec(i) 583 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 584 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 585 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 586 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 587 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 588 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 589 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 590 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 591 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 592 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 593 594 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 595 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 596 deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i)) 597 deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i)) 598 deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i)) 599 deq.bits.common.src := DontCare 600 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 601 602 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 603 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 604 rf.foreach(_.addr := psrc) 605 rf.foreach(_.srcType := srcType) 606 } 607 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 608 sink := source 609 } 610 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 611 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 612 613 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 614 deq.bits.common.perfDebugInfo.selectTime := GTimer() 615 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 616 } 617 618 private val deqShift = WireDefault(deqBeforeDly) 619 deqShift.zip(deqBeforeDly).foreach { 620 case (shifted, original) => 621 original.ready := shifted.ready // this will not cause combinational loop 622 shifted.bits.common.loadDependency.foreach( 623 _ := original.bits.common.loadDependency.get.map(_ << 1) 624 ) 625 } 626 io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) => 627 NewPipelineConnect( 628 deq, deqDly, deqDly.valid, 629 false.B, 630 Option("Scheduler2DataPathPipe") 631 ) 632 } 633 if(backendParams.debugEn) { 634 dontTouch(io.deqDelay) 635 } 636 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 637 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 638 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 639 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 640 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 641 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 642 } else if (wakeUpQueues(i).nonEmpty) { 643 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 644 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 645 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 646 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 647 } else { 648 wakeup.valid := false.B 649 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 650 wakeup.bits.is0Lat := 0.U 651 } 652 if (wakeUpQueues(i).nonEmpty) { 653 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 654 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 655 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 656 } 657 658 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 659 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 660 } 661 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 662 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 663 } 664 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 665 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 666 } 667 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 668 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 669 } 670 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 671 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 672 } 673 } 674 675 // Todo: better counter implementation 676 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 677 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 678 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 679 private val enqEntryValidCntDeq0 = PopCount( 680 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 681 ) 682 private val othersValidCntDeq0 = PopCount( 683 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 684 ) 685 private val enqEntryValidCntDeq1 = PopCount( 686 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 687 ) 688 private val othersValidCntDeq1 = PopCount( 689 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 690 ) 691 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 692 io.enq.map(_.bits.fuType).map(fuType => 693 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 694 } 695 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 696 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 697 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 +& enqValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 698 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 +& enqValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 699 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 700 for (i <- 0 until params.numEnq) { 701 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 702 } 703 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 704 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 705 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 706 } 707 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 708 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 709 710 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 711 io.status.empty := !Cat(validVec).orR 712 io.status.full := othersCanotIn 713 io.status.validCnt := PopCount(validVec) 714 715 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 716 Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 717 } 718 719 // issue perf counter 720 // enq count 721 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 722 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 723 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 724 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 725 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 726 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 727 // valid count 728 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 729 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 730 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 731 // only split when more than 1 func type 732 if (params.getFuCfgs.size > 0) { 733 for (t <- FuType.functionNameMap.keys) { 734 val fuName = FuType.functionNameMap(t) 735 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 736 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 737 } 738 } 739 } 740 // ready instr count 741 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 742 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 743 // only split when more than 1 func type 744 if (params.getFuCfgs.size > 0) { 745 for (t <- FuType.functionNameMap.keys) { 746 val fuName = FuType.functionNameMap(t) 747 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 748 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 749 } 750 } 751 } 752 753 // deq instr count 754 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 755 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 756 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 757 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 758 759 // deq instr data source count 760 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 761 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 762 }.reduce(_ +& _)) 763 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 764 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 765 }.reduce(_ +& _)) 766 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 767 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 768 }.reduce(_ +& _)) 769 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 770 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 771 }.reduce(_ +& _)) 772 773 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 774 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 775 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 776 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 777 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 778 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 779 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 780 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 781 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 782 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 783 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 784 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 785 786 // deq instr data source count for each futype 787 for (t <- FuType.functionNameMap.keys) { 788 val fuName = FuType.functionNameMap(t) 789 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 790 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 791 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 792 }.reduce(_ +& _)) 793 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 794 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 795 }.reduce(_ +& _)) 796 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 797 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 798 }.reduce(_ +& _)) 799 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 800 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 801 }.reduce(_ +& _)) 802 803 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 804 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 805 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 806 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 807 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 808 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 809 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 810 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 811 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 812 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 813 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 814 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 815 } 816 } 817 818 // cancel instr count 819 if (params.hasIQWakeUp) { 820 val cancelVec: Vec[Bool] = entries.io.cancel.get 821 XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2))) 822 XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1) 823 for (t <- FuType.functionNameMap.keys) { 824 val fuName = FuType.functionNameMap(t) 825 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 826 XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U })) 827 XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1) 828 } 829 } 830 } 831} 832 833class IssueQueueJumpBundle extends Bundle { 834 val pc = UInt(VAddrData().dataWidth.W) 835} 836 837class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 838 val fastMatch = UInt(backendParams.LduCnt.W) 839 val fastImm = UInt(12.W) 840} 841 842class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 843 844class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 845 extends IssueQueueImp(wrapper) 846{ 847 io.suggestName("none") 848 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 849 850 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 851 deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc) 852 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 853 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 854 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 855 deq.bits.common.predictInfo.foreach(x => { 856 x.target := DontCare 857 x.taken := deqEntryVec(i).bits.payload.pred_taken 858 }) 859 // for std 860 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 861 // for i2f 862 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 863 }} 864} 865 866class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 867 extends IssueQueueImp(wrapper) 868{ 869 s0_enqBits.foreach{ x => 870 x.srcType(3) := SrcType.vp // v0: mask src 871 x.srcType(4) := SrcType.vp // vl&vtype 872 } 873 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 874 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 875 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 876 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 877 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 878 }} 879} 880 881class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 882 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO)) 883 884 // TODO: is still needed? 885 val checkWait = new Bundle { 886 val stIssuePtr = Input(new SqPtr) 887 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 888 } 889 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 890 891 // load wakeup 892 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 893 894 // vector 895 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 896 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 897} 898 899class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 900 val memIO = Some(new IssueQueueMemBundle) 901} 902 903class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 904 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 905 906 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 907 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 908 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 909 910 io.suggestName("none") 911 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 912 private val memIO = io.memIO.get 913 914 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 915 916 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 917 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 918 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 919 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 920 slowResp.bits.fuType := DontCare 921 } 922 923 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 924 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 925 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 926 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 927 fastResp.bits.fuType := DontCare 928 } 929 930 // load wakeup 931 val loadWakeUpIter = memIO.loadWakeUp.iterator 932 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 933 if (param.hasLoadExu) { 934 require(wakeUpQueues(i).isEmpty) 935 val uop = loadWakeUpIter.next() 936 937 wakeup.valid := RegNext(uop.fire) 938 wakeup.bits.rfWen := RegNext(uop.bits.rfWen && uop.fire) 939 wakeup.bits.fpWen := RegNext(uop.bits.fpWen && uop.fire) 940 wakeup.bits.vecWen := RegNext(uop.bits.vecWen && uop.fire) 941 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 942 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 943 944 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.rfWen && uop.fire))) 945 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.fpWen && uop.fire))) 946 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := RegNext(uop.bits.vecWen && uop.fire))) 947 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 948 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 949 950 wakeup.bits.is0Lat := 0.U 951 } 952 } 953 require(!loadWakeUpIter.hasNext) 954 955 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 956 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 957 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 958 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 959 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 960 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 961 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 962 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 963 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 964 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 965 } 966} 967 968class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 969 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 970 971 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 972 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 973 974 io.suggestName("none") 975 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 976 private val memIO = io.memIO.get 977 978 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 979 980 def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = { 981 val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j)))) 982 val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j => 983 (if (j < i) !valid(j) || compareVec(i)(j) 984 else if (j == i) valid(i) 985 else !valid(j) || !compareVec(j)(i)) 986 )).andR)) 987 resultOnehot 988 } 989 990 val robIdxVec = entries.io.robIdx.get 991 val uopIdxVec = entries.io.uopIdx.get 992 val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec) 993 994 deqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR 995 deqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt 996 finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR && deqBeforeDly.head.ready 997 finalDeqSelOHVec.head := deqSelOHVec.head 998 999 s0_enqBits.foreach{ x => 1000 x.srcType(3) := SrcType.vp // v0: mask src 1001 x.srcType(4) := SrcType.vp // vl&vtype 1002 } 1003 1004 for (i <- entries.io.enq.indices) { 1005 entries.io.enq(i).bits.status match { case enqData => 1006 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1007 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1008 1009 // update blocked 1010 val isLsqHead = { 1011 s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get && 1012 s0_enqBits(i).sqIdx <= memIO.sqDeqPtr.get 1013 } 1014 enqData.blocked := !isLsqHead 1015 } 1016 } 1017 1018 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1019 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1020 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1021 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1022 slowResp.bits.fuType := DontCare 1023 slowResp.bits.uopIdx.get := 0.U // Todo 1024 } 1025 1026 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1027 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1028 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1029 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1030 fastResp.bits.fuType := DontCare 1031 fastResp.bits.uopIdx.get := 0.U // Todo 1032 } 1033 1034 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1035 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1036 1037 1038 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1039 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1040 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1041 if (params.isVecLduIQ) { 1042 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1043 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1044 } 1045 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1046 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1047 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1048 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1049 } 1050} 1051