1package xiangshan.backend.issue 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.utils._ 7 8trait IQConst{ 9 val iqSize = 8 10 val iqIdxWidth = log2Up(iqSize) 11} 12 13sealed abstract class IQBundle extends XSBundle with IQConst 14sealed abstract class IQModule extends XSModule with IQConst //with NeedImpl 15 16sealed class CmpInputBundle extends IQBundle{ 17 val instRdy = Input(Bool()) 18 val roqIdx = Input(UInt(RoqIdxWidth.W)) 19 val iqIdx = Input(UInt(iqIdxWidth.W)) 20 21 def apply(instRdy: Bool,roqIdx: UInt,iqIdx: UInt ) = { 22 this.instRdy := instRdy 23 this.roqIdx := roqIdx 24 this.iqIdx := iqIdx 25 this 26 } 27} 28 29 30sealed class CompareCircuitUnit extends IQModule { 31 val io = IO(new Bundle(){ 32 val in1 = new CmpInputBundle 33 val in2 = new CmpInputBundle 34 val out = Flipped(new CmpInputBundle) 35 }) 36 37 val roqIdx1 = io.in1.roqIdx 38 val roqIdx2 = io.in2.roqIdx 39 val iqIdx1 = io.in1.iqIdx 40 val iqIdx2 = io.in2.iqIdx 41 42 val inst1Rdy = io.in1.instRdy 43 val inst2Rdy = io.in2.instRdy 44 45 io.out.instRdy := inst1Rdy | inst2Rdy 46 io.out.roqIdx := roqIdx2 47 io.out.iqIdx := iqIdx2 48 49 when((inst1Rdy && !inst2Rdy) || (inst1Rdy && inst2Rdy && (roqIdx1 < roqIdx2))){ 50 io.out.roqIdx := roqIdx1 51 io.out.iqIdx := iqIdx1 52 } 53 54} 55 56object CCU{ 57 def apply(in1: CmpInputBundle, in2: CmpInputBundle) = { 58 val CCU = Module(new CompareCircuitUnit) 59 CCU.io.in1 <> in1 60 CCU.io.in2 <> in2 61 CCU.io.out 62 } 63} 64 65object ParallelSel { 66 def apply(iq: Seq[CmpInputBundle]): CmpInputBundle = { 67 iq match { 68 case Seq(a) => a 69 case Seq(a, b) => CCU(a, b) 70 case _ => 71 apply(Seq(apply(iq take iq.size/2), apply(iq drop iq.size/2))) 72 } 73 } 74} 75 76class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int = 0, val fixedDelay: Int = 1) extends IQModule { 77 78 val useBypass = bypassCnt > 0 79 80 val io = IO(new Bundle() { 81 // flush Issue Queue 82 val redirect = Flipped(ValidIO(new Redirect)) 83 84 // enq Ctrl sigs at dispatch-2 85 val enqCtrl = Flipped(DecoupledIO(new MicroOp)) 86 // enq Data at next cycle (regfile has 1 cycle latency) 87 val enqData = Flipped(ValidIO(new ExuInput)) 88 89 // broadcast selected uop to other issue queues which has bypasses 90 val selectedUop = if(useBypass) ValidIO(new MicroOp) else null 91 92 // send to exu 93 val deq = DecoupledIO(new ExuInput) 94 95 // listen to write back bus 96 val wakeUpPorts = Vec(wakeupCnt, Flipped(ValidIO(new ExuOutput))) 97 98 // use bypass uops to speculative wake-up 99 val bypassUops = if(useBypass) Vec(bypassCnt, Flipped(ValidIO(new MicroOp))) else null 100 val bypassData = if(useBypass) Vec(bypassCnt, Flipped(ValidIO(new ExuOutput))) else null 101 }) 102 //--------------------------------------------------------- 103 // Issue Queue 104 //--------------------------------------------------------- 105 106 //Tag Queue 107 val ctrlFlow = Mem(iqSize,new CtrlFlow) 108 val ctrlSig = Mem(iqSize,new CtrlSignals) 109 val brMask = Reg(Vec(iqSize, UInt(BrqSize.W))) 110 val brTag = Reg(Vec(iqSize, UInt(BrTagWidth.W))) 111 val validReg = RegInit(VecInit(Seq.fill(iqSize)(false.B))) 112 val validWillFalse= WireInit(VecInit(Seq.fill(iqSize)(false.B))) 113 val valid = validReg.asUInt & ~validWillFalse.asUInt 114 val src1Rdy = Reg(Vec(iqSize, Bool())) 115 val src2Rdy = Reg(Vec(iqSize, Bool())) 116 val src3Rdy = Reg(Vec(iqSize, Bool())) 117 val prfSrc1 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 118 val prfSrc2 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 119 val prfSrc3 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 120 val prfDest = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 121 val oldPDest = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 122 val freelistAllocPtr = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 123 val roqIdx = Reg(Vec(iqSize, UInt(RoqIdxWidth.W))) 124 125 val instRdy = WireInit(VecInit(List.tabulate(iqSize)(i => src1Rdy(i) && src2Rdy(i) && src3Rdy(i)&& valid(i)))) 126 127 128 //tag enqueue 129 val iqEmty = !valid.asUInt.orR 130 val iqFull = valid.asUInt.andR 131 val iqAllowIn = !iqFull 132 io.enqCtrl.ready := iqAllowIn 133 134 //enqueue pointer 135 val emptySlot = ~valid.asUInt 136 val enqueueSelect = PriorityEncoder(emptySlot) 137 //assert(!(io.enqCtrl.valid && io.redirect.valid),"enqueue valid should be false when redirect valid") 138 XSError(io.enqCtrl.valid && io.redirect.valid,"enqueue valid should be false when redirect valid") 139 val srcEnqRdy = WireInit(VecInit(false.B, false.B, false.B)) 140 141 srcEnqRdy(0) := Mux(io.enqCtrl.bits.ctrl.src1Type =/= SrcType.reg , true.B ,io.enqCtrl.bits.src1State === SrcState.rdy) 142 srcEnqRdy(1) := Mux(io.enqCtrl.bits.ctrl.src2Type =/= SrcType.reg , true.B ,io.enqCtrl.bits.src2State === SrcState.rdy) 143 //TODO: 144 if(fuTypeInt != FuType.fmac.litValue()){ srcEnqRdy(2) := true.B} 145 else{srcEnqRdy(2) := Mux(io.enqCtrl.bits.ctrl.src3Type =/= SrcType.reg , true.B ,io.enqCtrl.bits.src3State === SrcState.rdy)} 146 147 when (io.enqCtrl.fire()) { 148 ctrlFlow(enqueueSelect) := io.enqCtrl.bits.cf 149 ctrlSig(enqueueSelect) := io.enqCtrl.bits.ctrl 150 brMask(enqueueSelect) := io.enqCtrl.bits.brMask 151 brTag(enqueueSelect) := io.enqCtrl.bits.brTag 152 validReg(enqueueSelect) := true.B 153 src1Rdy(enqueueSelect) := srcEnqRdy(0) 154 src2Rdy(enqueueSelect) := srcEnqRdy(1) 155 src3Rdy(enqueueSelect) := srcEnqRdy(2) 156 prfSrc1(enqueueSelect) := io.enqCtrl.bits.psrc1 157 prfSrc2(enqueueSelect) := io.enqCtrl.bits.psrc2 158 prfSrc3(enqueueSelect) := io.enqCtrl.bits.psrc3 159 prfDest(enqueueSelect) := io.enqCtrl.bits.pdest 160 oldPDest(enqueueSelect) := io.enqCtrl.bits.old_pdest 161 freelistAllocPtr(enqueueSelect) := io.enqCtrl.bits.freelistAllocPtr 162 roqIdx(enqueueSelect) := io.enqCtrl.bits.roqIdx 163 XSDebug("[IQ enq]: enqSelect:%d | s1Rd:%d s2Rd:%d s3Rd:%d\n",enqueueSelect.asUInt, 164 (io.enqCtrl.bits.src1State === SrcState.rdy), 165 (io.enqCtrl.bits.src2State === SrcState.rdy), 166 (io.enqCtrl.bits.src3State === SrcState.rdy)) 167 168 } 169 170 //Data Queue 171 val src1Data = Reg(Vec(iqSize, UInt(XLEN.W))) 172 val src2Data = Reg(Vec(iqSize, UInt(XLEN.W))) 173 val src3Data = Reg(Vec(iqSize, UInt(XLEN.W))) 174 175 176 val enqSelNext = RegNext(enqueueSelect) 177 val enqFireNext = RegNext(io.enqCtrl.fire()) 178 179 // Read RegFile 180 //Ready data will written at next cycle 181 when (enqFireNext) { 182 when(src1Rdy(enqSelNext)){src1Data(enqSelNext) := io.enqData.bits.src1} 183 when(src2Rdy(enqSelNext)){src2Data(enqSelNext) := io.enqData.bits.src2} 184 when(src3Rdy(enqSelNext)){src3Data(enqSelNext) := io.enqData.bits.src3} 185 } 186 187 188 XSDebug("[Reg info-ENQ] enqSelNext:%d | enqFireNext:%d \n",enqSelNext,enqFireNext) 189 XSDebug("[IQ content] valid vr vf| pc insruction | src1rdy src1 | src2Rdy src2 | src3Rdy src3 | pdest \n") 190 for(i <- 0 to (iqSize -1)) { 191 val ins = ctrlFlow(i).instr 192 val pc = ctrlFlow(i).pc 193 XSDebug(valid(i), 194 "[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %x %x | %d valid|\n", 195 i.asUInt, valid(i), validReg(i), validWillFalse(i), pc,ins,src1Rdy(i), src1Data(i), 196 src2Rdy(i), src2Data(i),src3Rdy(i), src3Data(i),prfDest(i)) 197 XSDebug(validReg(i) && validWillFalse(i), 198 "[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %x %x | %d valid will be False|\n", 199 i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), 200 src2Rdy(i), src2Data(i),src3Rdy(i), src3Data(i),prfDest(i)) 201 XSDebug("[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %x %x | %d\n", 202 i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), 203 src2Rdy(i), src2Data(i),src3Rdy(i), src3Data(i),prfDest(i)) 204 } 205 // From Common Data Bus(wakeUpPort) 206 // chisel claims that firrtl will optimize Mux1H to and/or tree 207 // TODO: ignore ALU'cdb srcRdy, for byPass has done it 208 if(wakeupCnt > 0) { 209 val cdbValid = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).valid) 210 val cdbData = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).bits.data) 211 val cdbPdest = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).bits.uop.pdest) 212 213 val srcNum = 3 214 val prfSrc = List(prfSrc1, prfSrc2, prfSrc3) 215 val srcRdy = List(src1Rdy, src2Rdy, src3Rdy) 216 val srcData = List(src1Data, src2Data, src3Data) 217 val srcHitVec = List.tabulate(srcNum)(k => 218 List.tabulate(iqSize)(i => 219 List.tabulate(wakeupCnt)(j => 220 (prfSrc(k)(i) === cdbPdest(j)) && cdbValid(j)))) 221 val srcHit = List.tabulate(srcNum)(k => 222 List.tabulate(iqSize)(i => 223 ParallelOR(srcHitVec(k)(i)).asBool())) 224 // VecInit(srcHitVec(k)(i)).asUInt.orR)) 225 for(k <- 0 until srcNum){ 226 for(i <- 0 until iqSize)( when (valid(i)) { 227 when(!srcRdy(k)(i) && srcHit(k)(i)) { 228 srcRdy(k)(i) := true.B 229 // srcData(k)(i) := Mux1H(srcHitVec(k)(i), cdbData) 230 srcData(k)(i) := ParallelMux(srcHitVec(k)(i) zip cdbData) 231 } 232 }) 233 } 234 // From byPass [speculative] (just for ALU to listen to other ALU's res, include itself) 235 // just need Tag(Ctrl). send out Tag when Tag is decided. other ALUIQ listen to them and decide Tag 236 // byPassUops is one cycle before byPassDatas 237 if (bypassCnt > 0) { 238 val bypassPdest = List.tabulate(bypassCnt)(i => io.bypassUops(i).bits.pdest) 239 val bypassValid = List.tabulate(bypassCnt)(i => io.bypassUops(i).valid) // may only need valid not fire() 240 val bypassData = List.tabulate(bypassCnt)(i => io.bypassData(i).bits.data) 241 val srcBpHitVec = List.tabulate(srcNum)(k => 242 List.tabulate(iqSize)(i => 243 List.tabulate(bypassCnt)(j => 244 (prfSrc(k)(i) === bypassPdest(j)) && bypassValid(j)))) 245 val srcBpHit = List.tabulate(srcNum)(k => 246 List.tabulate(iqSize)(i => 247 ParallelOR(srcBpHitVec(k)(i)).asBool())) 248 // VecInit(srcBpHitVec(k)(i)).asUInt.orR)) 249 val srcBpHitVecNext = List.tabulate(srcNum)(k => 250 List.tabulate(iqSize)(i => 251 List.tabulate(bypassCnt)(j => RegNext(srcBpHitVec(k)(i)(j))))) 252 val srcBpHitNext = List.tabulate(srcNum)(k => 253 List.tabulate(iqSize)(i => 254 RegNext(srcBpHit(k)(i)))) 255 val srcBpData = List.tabulate(srcNum)(k => 256 List.tabulate(iqSize)(i => 257 ParallelMux(srcBpHitVecNext(k)(i) zip bypassData))) 258 // Mux1H(srcBpHitVecNext(k)(i), bypassData))) 259 for(k <- 0 until srcNum){ 260 for(i <- 0 until iqSize){ when (valid(i)) { 261 when(valid(i) && !srcRdy(k)(i) && srcBpHit(k)(i)) { srcRdy(k)(i) := true.B } 262 when(srcBpHitNext(k)(i)) { srcData(k)(i) := srcBpData(k)(i)} 263 }} 264 } 265 266 // Enqueue Bypass 267 val enqBypass = WireInit(VecInit(false.B, false.B, false.B)) 268 val enqBypassHitVec = List(List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc1 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire()), 269 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc2 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire()), 270 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc3 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire())) 271 val enqBypassHitVecNext = enqBypassHitVec.map(i => i.map(j => RegNext(j))) 272 enqBypass(0) := ParallelOR(enqBypassHitVec(0)) 273 enqBypass(1) := ParallelOR(enqBypassHitVec(1)) 274 enqBypass(2) := ParallelOR(enqBypassHitVec(2)) 275 when(enqBypass(0)) { src1Rdy(enqueueSelect) := true.B } 276 when(enqBypass(1)) { src2Rdy(enqueueSelect) := true.B } 277 when(enqBypass(2)) { src3Rdy(enqueueSelect) := true.B } 278 when(RegNext(enqBypass(0))) { src1Data(enqSelNext) := ParallelMux(enqBypassHitVecNext(0) zip bypassData)} 279 when(RegNext(enqBypass(1))) { src2Data(enqSelNext) := ParallelMux(enqBypassHitVecNext(1) zip bypassData)} 280 when(RegNext(enqBypass(2))) { src3Data(enqSelNext) := ParallelMux(enqBypassHitVecNext(2) zip bypassData)} 281 } 282 283 } 284 285 286 //--------------------------------------------------------- 287 // Select Circuit 288 //--------------------------------------------------------- 289 val selVec = List.tabulate(iqSize){ i => 290 Wire(new CmpInputBundle).apply(instRdy(i),roqIdx(i),i.U) 291 } 292 val selResult = ParallelSel(selVec) 293 XSDebug("[Sel Result] ResReady:%d || ResultId:%d\n",selResult.instRdy,selResult.iqIdx.asUInt) 294 //--------------------------------------------------------- 295 // Redirect Logic 296 //--------------------------------------------------------- 297 val expRedirect = io.redirect.valid && io.redirect.bits.isException 298 val brRedirect = io.redirect.valid && !io.redirect.bits.isException 299 300 List.tabulate(iqSize)( i => 301 when(brRedirect && (UIntToOH(io.redirect.bits.brTag) & brMask(i)).orR && validReg(i) ){ 302 validReg(i) := false.B 303 validWillFalse(i) := true.B 304 305 } .elsewhen(expRedirect) { 306 validReg(i) := false.B 307 validWillFalse(i) := true.B 308 } 309 ) 310 //--------------------------------------------------------- 311 // Dequeue Logic 312 //--------------------------------------------------------- 313 //hold the sel-index to wait for data 314 val selInstIdx = RegInit(0.U(iqIdxWidth.W)) 315 val selInstRdy = RegInit(false.B) 316 317 //issue the select instruction 318 val dequeueSelect = Wire(UInt(iqIdxWidth.W)) 319 dequeueSelect := selInstIdx 320 321 val brRedirectMaskMatch = (UIntToOH(io.redirect.bits.brTag) & brMask(dequeueSelect)).orR 322 val IQreadyGo = selInstRdy && !expRedirect && (!brRedirect || !brRedirectMaskMatch) 323 324 io.deq.valid := IQreadyGo 325 326 io.deq.bits.uop.cf := ctrlFlow(dequeueSelect) 327 io.deq.bits.uop.ctrl := ctrlSig(dequeueSelect) 328 io.deq.bits.uop.brMask := brMask(dequeueSelect) 329 io.deq.bits.uop.brTag := brTag(dequeueSelect) 330 331 io.deq.bits.uop.psrc1 := prfSrc1(dequeueSelect) 332 io.deq.bits.uop.psrc2 := prfSrc2(dequeueSelect) 333 io.deq.bits.uop.psrc3 := prfSrc3(dequeueSelect) 334 io.deq.bits.uop.pdest := prfDest(dequeueSelect) 335 io.deq.bits.uop.old_pdest := oldPDest(dequeueSelect) 336 io.deq.bits.uop.src1State := SrcState.rdy 337 io.deq.bits.uop.src2State := SrcState.rdy 338 io.deq.bits.uop.src3State := SrcState.rdy 339 io.deq.bits.uop.freelistAllocPtr := freelistAllocPtr(dequeueSelect) 340 io.deq.bits.uop.roqIdx := roqIdx(dequeueSelect) 341 342 io.deq.bits.src1 := src1Data(dequeueSelect) 343 io.deq.bits.src2 := src2Data(dequeueSelect) 344 io.deq.bits.src3 := src3Data(dequeueSelect) 345 346 XSDebug("[Reg Info-Sel] selInstRdy:%d || selIdx:%d\n",selInstRdy,selInstIdx.asUInt) 347 XSDebug(IQreadyGo,"[IQ dequeue] **dequeue fire:%d** roqIdx:%d dequeueSel:%d | src1Rd:%d src1:%d | src2Rd:%d src2:%d\n", io.deq.fire(), io.deq.bits.uop.roqIdx, dequeueSelect.asUInt, 348 (io.deq.bits.uop.src1State === SrcState.rdy), io.deq.bits.uop.psrc1, 349 (io.deq.bits.uop.src2State === SrcState.rdy), io.deq.bits.uop.psrc2 350 ) 351 352 //update the index register of instruction that can be issue, unless function unit not allow in 353 //then the issue will be stopped to wait the function unit 354 //clear the validBit of dequeued instruction in issuequeue 355 when(io.deq.fire()){ 356 validReg(dequeueSelect) := false.B 357 validWillFalse(dequeueSelect) := true.B 358 } 359 360 val selRegflush = expRedirect || (brRedirect && brRedirectMaskMatch) 361 362 selInstRdy := Mux(selRegflush,false.B,selResult.instRdy) 363 selInstIdx := Mux(selRegflush,0.U,selResult.iqIdx) 364 // SelectedUop (bypass / speculative) 365 if(useBypass) { 366 assert(fixedDelay==1) // only support fixedDelay is 1 now 367 def DelayPipe[T <: Data](a: T, delay: Int = 0) = { 368 // println(delay) 369 if(delay == 0) a 370 else { 371 val storage = Wire(VecInit(Seq.fill(delay+1)(a))) 372 // storage(0) := a 373 for(i <- 1 until delay) { 374 storage(i) := RegNext(storage(i-1)) 375 } 376 storage(delay) 377 } 378 } 379 val sel = io.selectedUop 380 val selIQIdx = selResult.iqIdx 381 val delayPipe = DelayPipe(VecInit(selResult.instRdy, prfDest(selIQIdx)), fixedDelay-1) 382 sel.bits := DontCare 383 sel.bits.pdest := delayPipe(fixedDelay-1)(1) 384 } 385} 386