xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 79b2c95bde886eeecf83c9214b2478f3ef89478e) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
12import xiangshan.backend.datapath.DataConfig._
13import xiangshan.backend.datapath.DataSource
14import xiangshan.backend.fu.{FuConfig, FuType}
15import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
16import xiangshan.backend.rob.RobPtr
17import xiangshan.backend.datapath.NewPipelineConnect
18
19class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
20  override def shouldBeInlined: Boolean = false
21
22  implicit val iqParams = params
23  lazy val module: IssueQueueImp = iqParams.schdType match {
24    case IntScheduler() => new IssueQueueIntImp(this)
25    case VfScheduler() => new IssueQueueVfImp(this)
26    case MemScheduler() =>
27      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
28      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
29      else new IssueQueueIntImp(this)
30    case _ => null
31  }
32}
33
34class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
35  val empty = Output(Bool())
36  val full = Output(Bool())
37  val validCnt = Output(UInt(log2Ceil(numEntries).W))
38  val leftVec = Output(Vec(numEnq + 1, Bool()))
39}
40
41class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
42
43class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
44  // Inputs
45  val flush = Flipped(ValidIO(new Redirect))
46  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
47
48  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
49  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
50  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
51  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
52  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
53  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
54  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
55  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
56  val og0Cancel = Input(ExuOH(backendParams.numExu))
57  val og1Cancel = Input(ExuOH(backendParams.numExu))
58  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
59  val finalBlock = Vec(params.numExu, Input(Bool()))
60
61  // Outputs
62  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
63  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
64  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
65
66  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
67  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
68}
69
70class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
71  extends LazyModuleImp(wrapper)
72  with HasXSParameter {
73
74  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
75    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
76    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
77    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}")
78
79  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
80  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
81  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
82  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
83  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
84  val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap)
85
86  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}")
87  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
88  lazy val io = IO(new IssueQueueIO())
89  // Modules
90
91  val entries = Module(new Entries)
92  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
93  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
94  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
95  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
96  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
97  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
98
99  class WakeupQueueFlush extends Bundle {
100    val redirect = ValidIO(new Redirect)
101    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
102    val og0Fail = Output(Bool())
103    val og1Fail = Output(Bool())
104    val finalFail = Output(Bool())
105  }
106
107  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
108    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
109    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
110    val ogFailFlush = stage match {
111      case 1 => flush.og0Fail
112      case 2 => flush.og1Fail
113      case 3 => flush.finalFail
114      case _ => false.B
115    }
116    redirectFlush || loadDependencyFlush || ogFailFlush
117  }
118
119  private def modificationFunc(exuInput: ExuInput): ExuInput = {
120    val newExuInput = WireDefault(exuInput)
121    newExuInput.loadDependency match {
122      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
123      case None =>
124    }
125    newExuInput
126  }
127
128  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource, Module(
129    new MultiWakeupQueue(new ExuInput(x), new WakeupQueueFlush, x.fuLatancySet, flushFunc, modificationFunc)
130  ))}
131  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
132
133  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
134  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
135  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
136  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
137  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
138  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
139  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
140  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
141  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
142  val s0_enqValidVec = io.enq.map(_.valid)
143  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
144  val s0_enqNotFlush = !io.flush.valid
145  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
146  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
147
148
149  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
150  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
151
152  val validVec = VecInit(entries.io.valid.asBools)
153  val canIssueVec = VecInit(entries.io.canIssue.asBools)
154  val clearVec = VecInit(entries.io.clear.asBools)
155  val deqFirstIssueVec = VecInit(entries.io.deq.map(_.isFirstIssue))
156
157  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
158  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
159  // (entryIdx)(srcIdx)(exuIdx)
160  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
161  val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer
162
163  // (deqIdx)(srcIdx)(exuIdx)
164  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
165  val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
166
167  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
168  val transEntryDeqVec = Wire(Vec(params.numEnq, ValidIO(new EntryBundle)))
169  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
170  val transSelVec = Wire(Vec(params.numEnq, UInt((params.numEntries-params.numEnq).W)))
171  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
172  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
173
174  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
175  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
176  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
177  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
178  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
179
180  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
181  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
182  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
183
184  /**
185    * Connection of [[entries]]
186    */
187  entries.io match { case entriesIO: EntriesIO =>
188    entriesIO.flush <> io.flush
189    entriesIO.wakeUpFromWB := io.wakeupFromWB
190    entriesIO.wakeUpFromIQ := io.wakeupFromIQ
191    entriesIO.og0Cancel := io.og0Cancel
192    entriesIO.og1Cancel := io.og1Cancel
193    entriesIO.ldCancel := io.ldCancel
194    entriesIO.enq.zipWithIndex.foreach { case (enq: ValidIO[EntryBundle], i) =>
195      enq.valid := s0_doEnqSelValidVec(i)
196      val numLsrc = s0_enqBits(i).srcType.size.min(enq.bits.status.srcType.size)
197      for (j <- 0 until numLsrc) {
198        enq.bits.status.srcState(j) := s0_enqBits(i).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(i).srcLoadDependency(j)), io.ldCancel)
199        enq.bits.status.psrc(j) := s0_enqBits(i).psrc(j)
200        enq.bits.status.srcType(j) := s0_enqBits(i).srcType(j)
201        enq.bits.status.dataSources(j).value := DataSource.reg
202        enq.bits.payload.debugInfo.enqRsTime := GTimer()
203      }
204      enq.bits.status.fuType := s0_enqBits(i).fuType
205      enq.bits.status.robIdx := s0_enqBits(i).robIdx
206      enq.bits.status.uopIdx.foreach(_ := s0_enqBits(i).uopIdx)
207      enq.bits.status.issueTimer := "b10".U
208      enq.bits.status.deqPortIdx := 0.U
209      enq.bits.status.issued := false.B
210      enq.bits.status.firstIssue := false.B
211      enq.bits.status.blocked := false.B
212
213      if (params.hasIQWakeUp) {
214        enq.bits.status.srcWakeUpL1ExuOH.get := 0.U.asTypeOf(enq.bits.status.srcWakeUpL1ExuOH.get)
215        enq.bits.status.srcTimer.get := 0.U.asTypeOf(enq.bits.status.srcTimer.get)
216        enq.bits.status.srcLoadDependency.foreach(_.zipWithIndex.foreach {
217          case (dep, srcIdx) =>
218            dep := VecInit(s0_enqBits(i).srcLoadDependency(srcIdx).map(x => x(x.getWidth - 2, 0) << 1))
219        })
220      }
221      if (params.inIntSchd && params.AluCnt > 0) {
222        // dirty code for lui+addi(w) fusion
223        val isLuiAddiFusion = s0_enqBits(i).isLUI32
224        val luiImm = Cat(s0_enqBits(i).lsrc(1), s0_enqBits(i).lsrc(0), s0_enqBits(i).imm(ImmUnion.maxLen - 1, 0))
225        enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(i).imm))
226      }
227      else if (params.inMemSchd && params.LduCnt > 0) {
228        // dirty code for fused_lui_load
229        val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(i).srcType(0)) && FuType.isLoad(s0_enqBits(i).fuType)
230        enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(i)), s0_enqBits(i).imm))
231      }
232      else {
233        enq.bits.imm.foreach(_ := s0_enqBits(i).imm)
234      }
235      enq.bits.payload := s0_enqBits(i)
236    }
237    entriesIO.deq.zipWithIndex.foreach { case (deq, i) =>
238      deq.enqEntryOldestSel := enqEntryOldestSel(i)
239      deq.othersEntryOldestSel := othersEntryOldestSel(i)
240      deq.subDeqRequest.foreach(_ := subDeqRequest.get)
241      deq.subDeqSelOH.foreach(_ := subDeqSelOHVec.get(i))
242      deq.deqReady := deqBeforeDly(i).ready
243      deq.deqSelOH.valid := deqSelValidVec(i)
244      deq.deqSelOH.bits := deqSelOHVec(i)
245    }
246    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
247      og0Resp.valid := io.og0Resp(i).valid
248      og0Resp.bits.robIdx := io.og0Resp(i).bits.robIdx
249      og0Resp.bits.uopIdx := io.og0Resp(i).bits.uopIdx
250      og0Resp.bits.dataInvalidSqIdx := io.og0Resp(i).bits.dataInvalidSqIdx
251      og0Resp.bits.respType := io.og0Resp(i).bits.respType
252      og0Resp.bits.rfWen := io.og0Resp(i).bits.rfWen
253      og0Resp.bits.fuType := io.og0Resp(i).bits.fuType
254    }
255    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
256      og1Resp.valid := io.og1Resp(i).valid
257      og1Resp.bits.robIdx := io.og1Resp(i).bits.robIdx
258      og1Resp.bits.uopIdx := io.og1Resp(i).bits.uopIdx
259      og1Resp.bits.dataInvalidSqIdx := io.og1Resp(i).bits.dataInvalidSqIdx
260      og1Resp.bits.respType := io.og1Resp(i).bits.respType
261      og1Resp.bits.rfWen := io.og1Resp(i).bits.rfWen
262      og1Resp.bits.fuType := io.og1Resp(i).bits.fuType
263    }
264    entriesIO.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, i) =>
265      finalIssueResp := io.finalIssueResp.get(i)
266    })
267    entriesIO.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
268      memAddrIssueResp := io.memAddrIssueResp.get(i)
269    })
270    transEntryDeqVec := entriesIO.transEntryDeqVec
271    deqEntryVec := entriesIO.deq.map(_.deqEntry)
272    fuTypeVec := entriesIO.fuType
273    cancelDeqVec := entriesIO.cancelDeqVec
274    transSelVec := entriesIO.transSelVec
275  }
276
277
278  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
279
280  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
281    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
282  ).reverse)
283
284  // if deq port can accept the uop
285  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
286    Cat(fuTypeVec.map(fuType =>
287      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
288    ).reverse)
289  }
290
291  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
292    fuTypeVec.map(fuType =>
293      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
294  }
295
296  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
297    val mergeFuBusy = {
298      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
299      else canIssueVec.asUInt
300    }
301    val mergeIntWbBusy = {
302      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
303      else mergeFuBusy
304    }
305    val mergeVfWbBusy = {
306      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
307      else mergeIntWbBusy
308    }
309    merge := mergeVfWbBusy
310  }
311
312  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
313    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
314  }
315
316  if (params.numDeq == 2) {
317    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
318  }
319
320  if (params.numDeq == 2 && params.deqFuSame) {
321    enqEntryOldestSel := DontCare
322
323    othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
324      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
325      canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
326    )
327    othersEntryOldestSel(1) := DontCare
328
329    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
330
331    val subDeqPolicy = Module(new DeqPolicy())
332    subDeqPolicy.io.request := subDeqRequest.get
333    subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
334    subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
335
336    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
337    deqSelValidVec(1) := subDeqSelValidVec.get(0)
338    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
339                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
340                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
341    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
342
343    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
344      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
345      selOH := deqOH
346    }
347  }
348  else {
349    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
350      enq = VecInit(s0_doEnqSelValidVec),
351      canIssue = VecInit(deqCanIssue.map(_(params.numEnq-1, 0)))
352    )
353
354    othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
355      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
356      canIssue = VecInit(deqCanIssue.map(_(params.numEntries-1, params.numEnq)))
357    )
358
359    deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
360      if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
361        selValid := false.B
362        selOH := 0.U.asTypeOf(selOH)
363      } else {
364        selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
365        selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, enqEntryOldestSel(i).valid && !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
366      }
367    }
368
369    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
370      selValid := deqValid && deqBeforeDly(i).ready
371      selOH := deqOH
372    }
373  }
374
375  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
376
377  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
378    deqResp.valid := finalDeqSelValidVec(i)
379    deqResp.bits.respType := RSFeedbackType.issueSuccess
380    deqResp.bits.robIdx := DontCare
381    deqResp.bits.dataInvalidSqIdx := DontCare
382    deqResp.bits.rfWen := DontCare
383    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
384    deqResp.bits.uopIdx := DontCare
385  }
386
387  //fuBusyTable
388  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
389    if(busyTableWrite.nonEmpty) {
390      val btwr = busyTableWrite.get
391      val btrd = busyTableRead.get
392      btwr.io.in.deqResp := toBusyTableDeqResp(i)
393      btwr.io.in.og0Resp := io.og0Resp(i)
394      btwr.io.in.og1Resp := io.og1Resp(i)
395      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
396      btrd.io.in.fuTypeRegVec := fuTypeVec
397      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
398    }
399    else {
400      fuBusyTableMask(i) := 0.U(params.numEntries.W)
401    }
402  }
403
404  //wbfuBusyTable write
405  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
406    if(busyTableWrite.nonEmpty) {
407      val btwr = busyTableWrite.get
408      val bt = busyTable.get
409      val dq = deqResp.get
410      btwr.io.in.deqResp := toBusyTableDeqResp(i)
411      btwr.io.in.og0Resp := io.og0Resp(i)
412      btwr.io.in.og1Resp := io.og1Resp(i)
413      bt := btwr.io.out.fuBusyTable
414      dq := btwr.io.out.deqRespSet
415    }
416  }
417
418  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
419    if (busyTableWrite.nonEmpty) {
420      val btwr = busyTableWrite.get
421      val bt = busyTable.get
422      val dq = deqResp.get
423      btwr.io.in.deqResp := toBusyTableDeqResp(i)
424      btwr.io.in.og0Resp := io.og0Resp(i)
425      btwr.io.in.og1Resp := io.og1Resp(i)
426      bt := btwr.io.out.fuBusyTable
427      dq := btwr.io.out.deqRespSet
428    }
429  }
430
431  //wbfuBusyTable read
432  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
433    if(busyTableRead.nonEmpty) {
434      val btrd = busyTableRead.get
435      val bt = busyTable.get
436      btrd.io.in.fuBusyTable := bt
437      btrd.io.in.fuTypeRegVec := fuTypeVec
438      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
439    }
440    else {
441      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
442    }
443  }
444  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
445    if (busyTableRead.nonEmpty) {
446      val btrd = busyTableRead.get
447      val bt = busyTable.get
448      btrd.io.in.fuBusyTable := bt
449      btrd.io.in.fuTypeRegVec := fuTypeVec
450      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
451    }
452    else {
453      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
454    }
455  }
456
457  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
458    val og0RespEach = io.og0Resp(i)
459    val og1RespEach = io.og1Resp(i)
460    wakeUpQueueOption.foreach {
461      wakeUpQueue =>
462        val flush = Wire(new WakeupQueueFlush)
463        flush.redirect := io.flush
464        flush.ldCancel := io.ldCancel
465        flush.og0Fail := io.og0Resp(i).valid && RSFeedbackType.isBlocked(io.og0Resp(i).bits.respType)
466        flush.og1Fail := io.og1Resp(i).valid && RSFeedbackType.isBlocked(io.og1Resp(i).bits.respType)
467        flush.finalFail := io.finalBlock(i)
468        wakeUpQueue.io.flush := flush
469        wakeUpQueue.io.enq.valid := deqBeforeDly(i).fire && {
470          deqBeforeDly(i).bits.common.rfWen.getOrElse(false.B) && deqBeforeDly(i).bits.common.pdest =/= 0.U ||
471          deqBeforeDly(i).bits.common.fpWen.getOrElse(false.B) ||
472          deqBeforeDly(i).bits.common.vecWen.getOrElse(false.B)
473        }
474        wakeUpQueue.io.enq.bits.uop := deqBeforeDly(i).bits.common
475        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
476        wakeUpQueue.io.og0IssueFail := flush.og0Fail
477        wakeUpQueue.io.og1IssueFail := flush.og1Fail
478    }
479  }
480
481  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
482    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
483    deq.bits.addrOH          := finalDeqSelOHVec(i)
484    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
485    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
486    deq.bits.common.fuType   := deqEntryVec(i).bits.status.fuType
487    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
488    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
489    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
490    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
491    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
492    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
493    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
494    deq.bits.common.dataSources.zip(finalDataSources(i)).zipWithIndex.foreach {
495      case ((sink, source), srcIdx) =>
496        sink.value := Mux(
497          SrcType.isXp(deqEntryVec(i).bits.status.srcType(srcIdx)) && deqEntryVec(i).bits.status.psrc(srcIdx) === 0.U,
498          DataSource.none,
499          source.value
500        )
501    }
502    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
503    deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i))
504    deq.bits.common.loadDependency.foreach(_ := deqEntryVec(i).bits.status.mergedLoadDependency.get)
505    deq.bits.common.deqLdExuIdx.foreach(_ := params.backendParam.getLdExuIdx(deq.bits.exuParams).U)
506    deq.bits.common.src := DontCare
507    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
508
509    deq.bits.rf.zip(deqEntryVec(i).bits.status.psrc).zip(deqEntryVec(i).bits.status.srcType).foreach { case ((rf, psrc), srcType) =>
510      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
511      rf.foreach(_.addr := psrc)
512      rf.foreach(_.srcType := srcType)
513    }
514    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcType).foreach { case (sink, source) =>
515      sink := source
516    }
517    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
518    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
519
520    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
521    deq.bits.common.perfDebugInfo.selectTime := GTimer()
522    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
523  }
524
525  private val deqShift = WireDefault(deqBeforeDly)
526  deqShift.zip(deqBeforeDly).foreach {
527    case (shifted, original) =>
528      original.ready := shifted.ready // this will not cause combinational loop
529      shifted.bits.common.loadDependency.foreach(
530        _ := original.bits.common.loadDependency.get.map(_ << 1)
531      )
532  }
533  io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) =>
534    NewPipelineConnect(
535      deq, deqDly, deqDly.valid,
536      false.B,
537      Option("Scheduler2DataPathPipe")
538    )
539  }
540  if(backendParams.debugEn) {
541    dontTouch(io.deqDelay)
542  }
543  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
544    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
545      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
546      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
547      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
548      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
549    } else if (wakeUpQueues(i).nonEmpty) {
550      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
551      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
552      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
553      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
554    } else {
555      wakeup.valid := false.B
556      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
557      wakeup.bits.is0Lat :=  0.U
558    }
559  }
560
561  // Todo: better counter implementation
562  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
563  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
564  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
565  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
566  for (i <- 0 until params.numEnq) {
567    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
568  }
569  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
570  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
571    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
572  }
573  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
574  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
575
576  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
577  io.status.empty := !Cat(validVec).orR
578  io.status.full := othersCanotIn
579  io.status.validCnt := PopCount(validVec)
580
581  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
582    Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
583  }
584
585  // issue perf counter
586  // enq count
587  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
588  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
589  // valid count
590  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
591  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
592  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
593  // only split when more than 1 func type
594  if (params.getFuCfgs.size > 0) {
595    for (t <- FuType.functionNameMap.keys) {
596      val fuName = FuType.functionNameMap(t)
597      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
598        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
599      }
600    }
601  }
602  // ready instr count
603  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
604  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
605  // only split when more than 1 func type
606  if (params.getFuCfgs.size > 0) {
607    for (t <- FuType.functionNameMap.keys) {
608      val fuName = FuType.functionNameMap(t)
609      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
610        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
611      }
612    }
613  }
614
615  // deq instr count
616  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
617  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
618  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
619  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
620
621  // deq instr data source count
622  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
623    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
624  }.reduce(_ +& _))
625  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
626    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
627  }.reduce(_ +& _))
628  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
629    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
630  }.reduce(_ +& _))
631  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
632    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
633  }.reduce(_ +& _))
634
635  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
636    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
637  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
638  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
639    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
640  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
641  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
642    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
643  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
644  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
645    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
646  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
647
648  // deq instr data source count for each futype
649  for (t <- FuType.functionNameMap.keys) {
650    val fuName = FuType.functionNameMap(t)
651    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
652      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
653        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
654      }.reduce(_ +& _))
655      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
656        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
657      }.reduce(_ +& _))
658      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
659        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
660      }.reduce(_ +& _))
661      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
662        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
663      }.reduce(_ +& _))
664
665      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
666        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
667      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
668      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
669        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
670      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
671      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
672        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
673      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
674      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
675        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
676      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
677    }
678  }
679
680  // cancel instr count
681  if (params.hasIQWakeUp) {
682    val cancelVec: Vec[Bool] = entries.io.cancel.get
683    XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)))
684    XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1)
685    for (t <- FuType.functionNameMap.keys) {
686      val fuName = FuType.functionNameMap(t)
687      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
688        XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }))
689        XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1)
690      }
691    }
692  }
693}
694
695class IssueQueueJumpBundle extends Bundle {
696  val pc = UInt(VAddrData().dataWidth.W)
697}
698
699class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
700  val fastMatch = UInt(backendParams.LduCnt.W)
701  val fastImm = UInt(12.W)
702}
703
704class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
705
706class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
707  extends IssueQueueImp(wrapper)
708{
709  io.suggestName("none")
710  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
711
712  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
713    deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc)
714    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
715    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
716    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
717    deq.bits.common.predictInfo.foreach(x => {
718      x.target := DontCare
719      x.taken := deqEntryVec(i).bits.payload.pred_taken
720    })
721    // for std
722    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
723    // for i2f
724    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
725  }}
726}
727
728class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
729  extends IssueQueueImp(wrapper)
730{
731  s0_enqBits.foreach{ x =>
732    x.srcType(3) := SrcType.vp // v0: mask src
733    x.srcType(4) := SrcType.vp // vl&vtype
734  }
735  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
736    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
737    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
738    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
739    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
740  }}
741}
742
743class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
744  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO))
745  val checkWait = new Bundle {
746    val stIssuePtr = Input(new SqPtr)
747    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
748  }
749  val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle))
750
751  // vector
752  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
753  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
754}
755
756class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
757  val memIO = Some(new IssueQueueMemBundle)
758}
759
760class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
761  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
762
763  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt + params.VlduCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
764    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
765  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
766
767  io.suggestName("none")
768  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
769  private val memIO = io.memIO.get
770
771  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
772
773  for (i <- io.enq.indices) {
774    val blockNotReleased = isAfter(io.enq(i).bits.sqIdx, memIO.checkWait.stIssuePtr)
775    val storeAddrWaitForIsIssuing = VecInit((0 until StorePipelineWidth).map(i => {
776      memIO.checkWait.memWaitUpdateReq.robIdx(i).valid &&
777        memIO.checkWait.memWaitUpdateReq.robIdx(i).bits.value === io.enq(i).bits.waitForRobIdx.value
778    })).asUInt.orR && !io.enq(i).bits.loadWaitStrict // is waiting for store addr ready
779    s0_enqBits(i).loadWaitBit := io.enq(i).bits.loadWaitBit && !storeAddrWaitForIsIssuing && blockNotReleased
780    // when have vpu
781    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
782      s0_enqBits(i).srcType(3) := SrcType.vp // v0: mask src
783      s0_enqBits(i).srcType(4) := SrcType.vp // vl&vtype
784    }
785  }
786
787  for (i <- entries.io.enq.indices) {
788    entries.io.enq(i).bits.status match { case enqData =>
789      enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
790      enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
791      enqData.mem.get.waitForStd := false.B
792      enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
793      enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
794      enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
795    }
796
797    entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
798      slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
799      slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
800      slowResp.bits.uopIdx           := DontCare
801      slowResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
802      slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
803      slowResp.bits.rfWen := DontCare
804      slowResp.bits.fuType := DontCare
805    }
806
807    entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
808      fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
809      fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
810      fastResp.bits.uopIdx           := DontCare
811      fastResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RSFeedbackType.fuIdle, memIO.feedbackIO(i).feedbackFast.bits.sourceType)
812      fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
813      fastResp.bits.rfWen := DontCare
814      fastResp.bits.fuType := DontCare
815    }
816
817    entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
818    entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
819  }
820
821  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
822    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
823    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
824    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
825    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
826    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
827    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
828    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
829    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
830    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
831    // when have vpu
832    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
833      deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
834      deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
835    }
836  }
837}
838
839class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
840  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
841
842  require((params.VstdCnt + params.VlduCnt + params.VstaCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
843
844  io.suggestName("none")
845  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
846  private val memIO = io.memIO.get
847
848  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
849    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
850    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
851      (if (j < i) !valid(j) || compareVec(i)(j)
852      else if (j == i) valid(i)
853      else !valid(j) || !compareVec(j)(i))
854    )).andR))
855    resultOnehot
856  }
857
858  val robIdxVec = entries.io.robIdx.get
859  val uopIdxVec = entries.io.uopIdx.get
860  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
861
862  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
863  finalDeqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
864
865  if (params.isVecMemAddrIQ) {
866    s0_enqBits.foreach{ x =>
867      x.srcType(3) := SrcType.vp // v0: mask src
868      x.srcType(4) := SrcType.vp // vl&vtype
869    }
870
871    for (i <- io.enq.indices) {
872      s0_enqBits(i).loadWaitBit := false.B
873    }
874
875    for (i <- entries.io.enq.indices) {
876      entries.io.enq(i).bits.status match { case enqData =>
877        enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
878        enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
879        enqData.mem.get.waitForStd := false.B
880        enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
881        enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
882        enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
883      }
884
885      entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
886        slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
887        slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
888        slowResp.bits.uopIdx           := DontCare
889        slowResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
890        slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
891        slowResp.bits.rfWen := DontCare
892        slowResp.bits.fuType := DontCare
893      }
894
895      entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
896        fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
897        fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
898        fastResp.bits.uopIdx           := DontCare
899        fastResp.bits.respType         := memIO.feedbackIO(i).feedbackFast.bits.sourceType
900        fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
901        fastResp.bits.rfWen := DontCare
902        fastResp.bits.fuType := DontCare
903      }
904
905      entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
906      entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
907    }
908  }
909
910  for (i <- entries.io.enq.indices) {
911    entries.io.enq(i).bits.status match { case enqData =>
912      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
913      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
914    }
915  }
916
917  entries.io.fromLsq.get.sqDeqPtr := memIO.sqDeqPtr.get
918  entries.io.fromLsq.get.lqDeqPtr := memIO.lqDeqPtr.get
919
920  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
921    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
922    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.payload.lqIdx)
923    if (params.isVecLdAddrIQ) {
924      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
925      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
926    }
927    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
928    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
929    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
930    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
931  }
932}
933