1package xiangshan.backend.issue 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6 7trait IQConst{ 8 val iqSize = 8 9 10} 11 12class IssueQueue(val fuTypeInt: BigInt, wakeupCnt: Int, val bypassCnt: Int) extends XSModule with NeedImpl { 13 14 val useBypass = bypassCnt > 0 15 16 val io = IO(new Bundle() { 17 // flush Issue Queue 18 val redirect = Flipped(ValidIO(new Redirect)) 19 20 // enq Ctrl sigs at dispatch-2 21 val enqCtrl = Flipped(DecoupledIO(new MicroOp)) 22 // enq Data at next cycle (regfile has 1 cycle latency) 23 val enqData = Flipped(ValidIO(new ExuInput)) 24 25 // broadcast selected uop to other issue queues which has bypasses 26 val selectedUop = if(useBypass) DecoupledIO(new MicroOp) else null 27 28 // send to exu 29 val deq = DecoupledIO(new ExuInput) 30 31 // listen to write back bus 32 val wakeUpPorts = Vec(wakeupCnt, Flipped(DecoupledIO(new ExuOutput))) 33 34 // use bypass uops to speculative wake-up 35 val bypassUops = if(useBypass) Vec(bypassCnt, Flipped(DecoupledIO(new MicroOp))) else null 36 val bypassData = if(useBypass) Vec(bypassCnt, Flipped(DecoupledIO(new ExuOutput))) else null 37 }) 38 //--------------------------------------------------------- 39 // Issue Queue 40 //--------------------------------------------------------- 41 42 //Tag Queue 43 val ctrlFlow = Mem(iqSize,new CtrlFlow) 44 val ctrlSig = Mem(iqSize,new CtrlSignals) 45 val valid = RegInit(VecInit(Seq.fill(iqSize)(false.B))) 46 val src1Rdy = RegInit(VecInit(Seq.fill(iqSize)(false.B))) 47 val src2Rdy = RegInit(VecInit(Seq.fill(iqSize)(false.B))) 48 val brMask = RegInit(VecInit(Seq.fill(iqSize)(0.U(BrqSize.W)))) 49 val prfSrc1 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 50 val prfSrc2 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 51 val roqIdx = Reg(Vec(iqSize, UInt(RoqIdxWidth.W))) 52 53 //tag enqueue 54 val iqEmty = !valid.asUInt.orR 55 val iqFull = valid.asUInt.andR 56 val iqAllowIn = !iqFull 57 io.enqCtrl.ready := iqAllowIn 58 59 //enqueue pointer 60 val emptySlot = ~valid.asUInt 61 val enqueueSelect = PriorityEncoder(emptySlot) 62 63 when(io.enqCtrl.fire()){ 64 ctrlFlow(enqueueSelect) := io.enqCtrl.bits.cf 65 ctrlSig(enqueueSelect) := io.enqCtrl.bits.ctrl 66 valid(enqueueSelect) := true.B 67 prfSrc1(enqueueSelect) := io.enqCtrl.bits.psrc1 68 prfSrc2(enqueueSelect) := io.enqCtrl.bits.psrc2 69 src1Rdy(enqueueSelect) := io.enqCtrl.bits.src1State === SrcState.rdy 70 src2Rdy(enqueueSelect) := io.enqCtrl.bits.src2State === SrcState.rdy 71 brMask(enqueueSelect) := io.enqCtrl.bits.brMask 72 } 73 74 //Data Queue 75 val src1Data = Reg(Vec(iqSize, UInt(XLEN.W))) 76 val src2Data = Reg(Vec(iqSize, UInt(XLEN.W))) 77 78 79 80 //--------------------------------------------------------- 81 // Select Circuit 82 //--------------------------------------------------------- 83 84 85} 86