1package xiangshan.backend.issue 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6 7trait IQConst{ 8 val iqSize = 4 9 10} 11 12class IssueQueue(val fuTypeInt: BigInt, wakeupCnt: Int, val bypassCnt: Int) extends XSModule with NeedImpl { 13 14 val useBypass = bypassCnt > 0 15 16 val io = IO(new Bundle() { 17 // flush Issue Queue 18 val redirect = Flipped(ValidIO(new Redirect)) 19 20 // enq Ctrl sigs at dispatch-2 21 val enqCtrl = Flipped(DecoupledIO(new MicroOp)) 22 // enq Data at next cycle (regfile has 1 cycle latency) 23 val enqData = Flipped(ValidIO(new ExuInput)) 24 25 // broadcast selected uop to other issue queues which has bypasses 26 val selectedUop = if(useBypass) DecoupledIO(new MicroOp) else null 27 28 // send to exu 29 val deq = DecoupledIO(new ExuInput) 30 31 // listen to write back bus 32 val wakeUpPorts = Vec(wakeupCnt, Flipped(DecoupledIO(new ExuOutput))) 33 34 // use bypass uops to speculative wake-up 35 val bypassUops = if(useBypass) Vec(bypassCnt, Flipped(DecoupledIO(new MicroOp))) else null 36 val bypassData = if(useBypass) Vec(bypassCnt, Flipped(DecoupledIO(new ExuOutput))) else null 37 }) 38 //--------------------------------------------------------- 39 // Issue Queue 40 //--------------------------------------------------------- 41 val valid = RegInit(VecInit(Seq.fill(iqSize)(false.B))) 42 val src1Rdy = RegInit(VecInit(Seq.fill(iqSize)(false.B))) 43 val src2Rdy = RegInit(VecInit(Seq.fill(iqSize)(false.B))) 44 val brMask = RegInit(VecInit(Seq.fill(iqSize)(0.U(robInstCapacity.W)))) 45 val prfSrc1 = Reg(Vec(iqSize, UInt(prfAddrWidth.W))) 46 val prfSrc2 = Reg(Vec(iqSize, UInt(prfAddrWidth.W))) 47 val src1 = Reg(Vec(iqSize, UInt(XLEN.W))) 48 val src2 = Reg(Vec(iqSize, UInt(XLEN.W))) 49 50} 51