1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne, GatedValidRegNext} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case VfScheduler() => new IssueQueueVfImp(this) 27 case MemScheduler() => 28 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 29 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 30 else new IssueQueueIntImp(this) 31 case _ => null 32 } 33} 34 35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 36 val empty = Output(Bool()) 37 val full = Output(Bool()) 38 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 39 val leftVec = Output(Vec(numEnq + 1, Bool())) 40} 41 42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 43 44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 45 // Inputs 46 val flush = Flipped(ValidIO(new Redirect)) 47 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 48 49 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 50 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 52 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 55 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 56 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 57 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 58 val og0Cancel = Input(ExuOH(backendParams.numExu)) 59 val og1Cancel = Input(ExuOH(backendParams.numExu)) 60 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 61 62 // Outputs 63 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 64 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 65 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 66 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 67 68 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 69 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 70} 71 72class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 73 extends LazyModuleImp(wrapper) 74 with HasXSParameter { 75 76 override def desiredName: String = s"${params.getIQName}" 77 78 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 79 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 80 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 81 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 82 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 83 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 84 85 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 86 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 87 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 88 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 89 90 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 91 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 92 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 93 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 94 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 95 96 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 97 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 98 lazy val io = IO(new IssueQueueIO()) 99 100 // Modules 101 val entries = Module(new Entries) 102 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 103 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 104 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 105 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 106 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 107 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 108 109 class WakeupQueueFlush extends Bundle { 110 val redirect = ValidIO(new Redirect) 111 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 112 val og0Fail = Output(Bool()) 113 val og1Fail = Output(Bool()) 114 } 115 116 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 117 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 118 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 119 val ogFailFlush = stage match { 120 case 1 => flush.og0Fail 121 case 2 => flush.og1Fail 122 case _ => false.B 123 } 124 redirectFlush || loadDependencyFlush || ogFailFlush 125 } 126 127 private def modificationFunc(exuInput: ExuInput): ExuInput = { 128 val newExuInput = WireDefault(exuInput) 129 newExuInput.loadDependency match { 130 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 131 case None => 132 } 133 newExuInput 134 } 135 136 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 137 val lastExuInput = WireDefault(exuInput) 138 val newExuInput = WireDefault(newInput) 139 newExuInput.elements.foreach { case (name, data) => 140 if (lastExuInput.elements.contains(name)) { 141 data := lastExuInput.elements(name) 142 } 143 } 144 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 145 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 146 } 147 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 148 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 149 } 150 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 151 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 152 } 153 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 154 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 155 } 156 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 157 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 158 } 159 newExuInput 160 } 161 162 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 163 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 164 ))} 165 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 166 167 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 168 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 169 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 170 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 171 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 172 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 173 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 174 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 175 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 176 val s0_enqValidVec = io.enq.map(_.valid) 177 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 178 val s0_enqNotFlush = !io.flush.valid 179 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 180 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 181 182 183 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 184 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 185 186 val validVec = VecInit(entries.io.valid.asBools) 187 val canIssueVec = VecInit(entries.io.canIssue.asBools) 188 dontTouch(canIssueVec) 189 val deqFirstIssueVec = entries.io.isFirstIssue 190 191 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 192 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 193 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 194 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 195 // (entryIdx)(srcIdx)(exuIdx) 196 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 197 val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer 198 199 // (deqIdx)(srcIdx)(exuIdx) 200 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 201 val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 202 203 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 204 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 205 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 206 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 207 208 //deq 209 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 210 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 211 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 212 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 213 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 214 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 215 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 216 217 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 218 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 219 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 220 221 //trans 222 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 223 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 224 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 225 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 226 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 227 228 /** 229 * Connection of [[entries]] 230 */ 231 entries.io match { case entriesIO: EntriesIO => 232 entriesIO.flush := io.flush 233 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 234 enq.valid := s0_doEnqSelValidVec(enqIdx) 235 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 236 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 237 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 238 for(j <- 0 until numLsrc) { 239 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 240 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 241 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 242 enq.bits.status.srcStatus(j).dataSources.value := Mux( 243 SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 244 DataSource.zero, 245 Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg) 246 ) 247 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1)) 248 if(params.hasIQWakeUp) { 249 enq.bits.status.srcStatus(j).srcTimer.get := 0.U(3.W) 250 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 251 } 252 } 253 enq.bits.status.blocked := false.B 254 enq.bits.status.issued := false.B 255 enq.bits.status.firstIssue := false.B 256 enq.bits.status.issueTimer := "b11".U 257 enq.bits.status.deqPortIdx := 0.U 258 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 259 enq.bits.payload := s0_enqBits(enqIdx) 260 } 261 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 262 og0Resp := io.og0Resp(i) 263 } 264 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 265 og1Resp := io.og1Resp(i) 266 } 267 if (params.inVfSchd) { 268 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 269 og2Resp := io.og2Resp.get(i) 270 } 271 } 272 if (params.isLdAddrIQ || params.isHyAddrIQ) { 273 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 274 finalIssueResp := io.finalIssueResp.get(i) 275 } 276 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 277 memAddrIssueResp := io.memAddrIssueResp.get(i) 278 } 279 } 280 for(deqIdx <- 0 until params.numDeq) { 281 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 282 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 283 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 284 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 285 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 286 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 287 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 288 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 289 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 290 } 291 entriesIO.wakeUpFromWB := io.wakeupFromWB 292 entriesIO.wakeUpFromIQ := io.wakeupFromIQ 293 entriesIO.og0Cancel := io.og0Cancel 294 entriesIO.og1Cancel := io.og1Cancel 295 entriesIO.ldCancel := io.ldCancel 296 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 297 //output 298 fuTypeVec := entriesIO.fuType 299 deqEntryVec := entriesIO.deqEntry 300 cancelDeqVec := entriesIO.cancelDeqVec 301 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 302 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 303 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 304 } 305 306 307 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 308 309 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 310 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 311 ).reverse) 312 313 // if deq port can accept the uop 314 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 315 Cat(fuTypeVec.map(fuType => 316 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 317 ).reverse) 318 } 319 320 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 321 fuTypeVec.map(fuType => 322 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 323 } 324 325 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 326 val mergeFuBusy = { 327 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 328 else canIssueVec.asUInt 329 } 330 val mergeIntWbBusy = { 331 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 332 else mergeFuBusy 333 } 334 val mergeVfWbBusy = { 335 if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i)) 336 else mergeIntWbBusy 337 } 338 merge := mergeVfWbBusy 339 } 340 341 deqCanIssue.zipWithIndex.foreach { case (req, i) => 342 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 343 } 344 dontTouch(fuTypeVec) 345 dontTouch(canIssueMergeAllBusy) 346 dontTouch(deqCanIssue) 347 348 if (params.numDeq == 2) { 349 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 350 } 351 352 if (params.numDeq == 2 && params.deqFuSame) { 353 val subDeqPolicy = Module(new DeqPolicy()) 354 355 enqEntryOldestSel := DontCare 356 357 if (params.isAllComp || params.isAllSimp) { 358 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 359 enq = othersEntryEnqSelVec.get, 360 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 361 ) 362 othersEntryOldestSel(1) := DontCare 363 364 subDeqPolicy.io.request := subDeqRequest.get 365 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 366 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 367 } 368 else { 369 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 370 simpAgeDetectRequest.get(1) := DontCare 371 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 372 if (params.numEnq == 2) { 373 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 374 } 375 376 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 377 enq = simpEntryEnqSelVec.get, 378 canIssue = simpAgeDetectRequest.get 379 ) 380 381 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 382 enq = compEntryEnqSelVec.get, 383 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 384 ) 385 compEntryOldestSel.get(1) := DontCare 386 387 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 388 othersEntryOldestSel(0).bits := Cat( 389 compEntryOldestSel.get(0).bits, 390 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 391 ) 392 othersEntryOldestSel(1) := DontCare 393 394 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 395 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 396 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 397 } 398 399 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 400 401 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 402 deqSelValidVec(1) := subDeqSelValidVec.get(0) 403 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 404 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 405 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 406 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 407 408 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 409 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 410 selOH := deqOH 411 } 412 } 413 else { 414 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 415 enq = VecInit(s0_doEnqSelValidVec), 416 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 417 ) 418 419 if (params.isAllComp || params.isAllSimp) { 420 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 421 enq = othersEntryEnqSelVec.get, 422 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 423 ) 424 425 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 426 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 427 selValid := false.B 428 selOH := 0.U.asTypeOf(selOH) 429 } else { 430 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 431 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 432 } 433 } 434 } 435 else { 436 othersEntryOldestSel := DontCare 437 438 deqCanIssue.zipWithIndex.foreach { case (req, i) => 439 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 440 } 441 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 442 if (params.numEnq == 2) { 443 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 444 } 445 446 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 447 enq = simpEntryEnqSelVec.get, 448 canIssue = simpAgeDetectRequest.get 449 ) 450 451 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 452 enq = compEntryEnqSelVec.get, 453 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 454 ) 455 456 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 457 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 458 selValid := false.B 459 selOH := 0.U.asTypeOf(selOH) 460 } else { 461 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 462 selOH := Cat( 463 compEntryOldestSel.get(i).bits, 464 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 465 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 466 ) 467 } 468 } 469 } 470 471 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 472 selValid := deqValid && deqBeforeDly(i).ready 473 selOH := deqOH 474 } 475 } 476 477 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 478 479 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 480 deqResp.valid := finalDeqSelValidVec(i) 481 deqResp.bits.resp := RespType.success 482 deqResp.bits.robIdx := DontCare 483 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 484 deqResp.bits.uopIdx.foreach(_ := DontCare) 485 } 486 487 //fuBusyTable 488 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 489 if(busyTableWrite.nonEmpty) { 490 val btwr = busyTableWrite.get 491 val btrd = busyTableRead.get 492 btwr.io.in.deqResp := toBusyTableDeqResp(i) 493 btwr.io.in.og0Resp := io.og0Resp(i) 494 btwr.io.in.og1Resp := io.og1Resp(i) 495 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 496 btrd.io.in.fuTypeRegVec := fuTypeVec 497 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 498 } 499 else { 500 fuBusyTableMask(i) := 0.U(params.numEntries.W) 501 } 502 } 503 504 //wbfuBusyTable write 505 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 506 if(busyTableWrite.nonEmpty) { 507 val btwr = busyTableWrite.get 508 val bt = busyTable.get 509 val dq = deqResp.get 510 btwr.io.in.deqResp := toBusyTableDeqResp(i) 511 btwr.io.in.og0Resp := io.og0Resp(i) 512 btwr.io.in.og1Resp := io.og1Resp(i) 513 bt := btwr.io.out.fuBusyTable 514 dq := btwr.io.out.deqRespSet 515 } 516 } 517 518 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 519 if (busyTableWrite.nonEmpty) { 520 val btwr = busyTableWrite.get 521 val bt = busyTable.get 522 val dq = deqResp.get 523 btwr.io.in.deqResp := toBusyTableDeqResp(i) 524 btwr.io.in.og0Resp := io.og0Resp(i) 525 btwr.io.in.og1Resp := io.og1Resp(i) 526 bt := btwr.io.out.fuBusyTable 527 dq := btwr.io.out.deqRespSet 528 } 529 } 530 531 //wbfuBusyTable read 532 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 533 if(busyTableRead.nonEmpty) { 534 val btrd = busyTableRead.get 535 val bt = busyTable.get 536 btrd.io.in.fuBusyTable := bt 537 btrd.io.in.fuTypeRegVec := fuTypeVec 538 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 539 } 540 else { 541 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 542 } 543 } 544 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 545 if (busyTableRead.nonEmpty) { 546 val btrd = busyTableRead.get 547 val bt = busyTable.get 548 btrd.io.in.fuBusyTable := bt 549 btrd.io.in.fuTypeRegVec := fuTypeVec 550 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 551 } 552 else { 553 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 554 } 555 } 556 557 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 558 wakeUpQueueOption.foreach { 559 wakeUpQueue => 560 val flush = Wire(new WakeupQueueFlush) 561 flush.redirect := io.flush 562 flush.ldCancel := io.ldCancel 563 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 564 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 565 wakeUpQueue.io.flush := flush 566 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 567 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 568 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 569 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 570 } 571 } 572 573 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 574 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 575 deq.bits.addrOH := finalDeqSelOHVec(i) 576 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 577 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 578 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 579 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 580 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 581 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 582 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 583 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 584 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 585 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 586 587 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 588 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 589 deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i)) 590 deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i)) 591 deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i)) 592 deq.bits.common.src := DontCare 593 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 594 595 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 596 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 597 rf.foreach(_.addr := psrc) 598 rf.foreach(_.srcType := srcType) 599 } 600 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 601 sink := source 602 } 603 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 604 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 605 606 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 607 deq.bits.common.perfDebugInfo.selectTime := GTimer() 608 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 609 } 610 611 private val deqShift = WireDefault(deqBeforeDly) 612 deqShift.zip(deqBeforeDly).foreach { 613 case (shifted, original) => 614 original.ready := shifted.ready // this will not cause combinational loop 615 shifted.bits.common.loadDependency.foreach( 616 _ := original.bits.common.loadDependency.get.map(_ << 1) 617 ) 618 } 619 io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) => 620 NewPipelineConnect( 621 deq, deqDly, deqDly.valid, 622 false.B, 623 Option("Scheduler2DataPathPipe") 624 ) 625 } 626 if(backendParams.debugEn) { 627 dontTouch(io.deqDelay) 628 } 629 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 630 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 631 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 632 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 633 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 634 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 635 } else if (wakeUpQueues(i).nonEmpty) { 636 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 637 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 638 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 639 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 640 } else { 641 wakeup.valid := false.B 642 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 643 wakeup.bits.is0Lat := 0.U 644 } 645 if (wakeUpQueues(i).nonEmpty) { 646 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 647 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 648 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 649 } 650 651 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 652 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 653 } 654 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 655 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 656 } 657 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 658 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 659 } 660 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 661 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 662 } 663 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 664 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 665 } 666 } 667 668 // Todo: better counter implementation 669 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 670 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 671 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 672 private val enqEntryValidCntDeq0 = PopCount( 673 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 674 ) 675 private val othersValidCntDeq0 = PopCount( 676 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 677 ) 678 private val enqEntryValidCntDeq1 = PopCount( 679 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 680 ) 681 private val othersValidCntDeq1 = PopCount( 682 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 683 ) 684 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 685 io.enq.map(_.bits.fuType).map(fuType => 686 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 687 } 688 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 689 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 690 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 691 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 692 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 693 for (i <- 0 until params.numEnq) { 694 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 695 } 696 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 697 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 698 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 699 } 700 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 701 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 702 703 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 704 io.status.empty := !Cat(validVec).orR 705 io.status.full := othersCanotIn 706 io.status.validCnt := PopCount(validVec) 707 708 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 709 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 710 } 711 712 // issue perf counter 713 // enq count 714 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 715 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 716 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 717 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 718 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 719 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 720 // valid count 721 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 722 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 723 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 724 // only split when more than 1 func type 725 if (params.getFuCfgs.size > 0) { 726 for (t <- FuType.functionNameMap.keys) { 727 val fuName = FuType.functionNameMap(t) 728 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 729 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 730 } 731 } 732 } 733 // ready instr count 734 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 735 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 736 // only split when more than 1 func type 737 if (params.getFuCfgs.size > 0) { 738 for (t <- FuType.functionNameMap.keys) { 739 val fuName = FuType.functionNameMap(t) 740 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 741 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 742 } 743 } 744 } 745 746 // deq instr count 747 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 748 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 749 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 750 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 751 752 // deq instr data source count 753 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 754 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 755 }.reduce(_ +& _)) 756 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 757 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 758 }.reduce(_ +& _)) 759 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 760 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 761 }.reduce(_ +& _)) 762 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 763 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 764 }.reduce(_ +& _)) 765 766 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 767 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 768 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 769 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 770 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 771 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 772 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 773 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 774 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 775 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 776 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 777 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 778 779 // deq instr data source count for each futype 780 for (t <- FuType.functionNameMap.keys) { 781 val fuName = FuType.functionNameMap(t) 782 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 783 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 784 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 785 }.reduce(_ +& _)) 786 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 787 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 788 }.reduce(_ +& _)) 789 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 790 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 791 }.reduce(_ +& _)) 792 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 793 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 794 }.reduce(_ +& _)) 795 796 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 797 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 798 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 799 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 800 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 801 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 802 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 803 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 804 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 805 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 806 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 807 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 808 } 809 } 810 811 // cancel instr count 812 if (params.hasIQWakeUp) { 813 val cancelVec: Vec[Bool] = entries.io.cancel.get 814 XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2))) 815 XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1) 816 for (t <- FuType.functionNameMap.keys) { 817 val fuName = FuType.functionNameMap(t) 818 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 819 XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U })) 820 XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1) 821 } 822 } 823 } 824} 825 826class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 827 val fastMatch = UInt(backendParams.LduCnt.W) 828 val fastImm = UInt(12.W) 829} 830 831class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 832 833class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 834 extends IssueQueueImp(wrapper) 835{ 836 io.suggestName("none") 837 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 838 839 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 840 deq.bits.common.pc.foreach(_ := DontCare) 841 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 842 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 843 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 844 deq.bits.common.predictInfo.foreach(x => { 845 x.target := DontCare 846 x.taken := deqEntryVec(i).bits.payload.pred_taken 847 }) 848 // for std 849 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 850 // for i2f 851 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 852 }} 853} 854 855class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 856 extends IssueQueueImp(wrapper) 857{ 858 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 859 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 860 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 861 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 862 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 863 }} 864} 865 866class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 867 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO)) 868 869 // TODO: is still needed? 870 val checkWait = new Bundle { 871 val stIssuePtr = Input(new SqPtr) 872 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 873 } 874 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 875 876 // load wakeup 877 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 878 879 // vector 880 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 881 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 882} 883 884class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 885 val memIO = Some(new IssueQueueMemBundle) 886} 887 888class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 889 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 890 891 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 892 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 893 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 894 895 io.suggestName("none") 896 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 897 private val memIO = io.memIO.get 898 899 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 900 901 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 902 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 903 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 904 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 905 slowResp.bits.fuType := DontCare 906 } 907 908 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 909 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 910 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 911 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 912 fastResp.bits.fuType := DontCare 913 } 914 915 // load wakeup 916 val loadWakeUpIter = memIO.loadWakeUp.iterator 917 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 918 if (param.hasLoadExu) { 919 require(wakeUpQueues(i).isEmpty) 920 val uop = loadWakeUpIter.next() 921 922 wakeup.valid := GatedValidRegNext(uop.fire) 923 wakeup.bits.rfWen := GatedValidRegNext(uop.bits.rfWen && uop.fire) 924 wakeup.bits.fpWen := GatedValidRegNext(uop.bits.fpWen && uop.fire) 925 wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire) 926 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 927 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 928 929 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen && uop.fire))) 930 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen && uop.fire))) 931 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire))) 932 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 933 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 934 935 wakeup.bits.is0Lat := 0.U 936 } 937 } 938 require(!loadWakeUpIter.hasNext) 939 940 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 941 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 942 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 943 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 944 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 945 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 946 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 947 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 948 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 949 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 950 } 951} 952 953class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 954 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 955 956 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 957 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 958 959 io.suggestName("none") 960 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 961 private val memIO = io.memIO.get 962 963 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 964 965 def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = { 966 val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j)))) 967 val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j => 968 (if (j < i) !valid(j) || compareVec(i)(j) 969 else if (j == i) valid(i) 970 else !valid(j) || !compareVec(j)(i)) 971 )).andR)) 972 resultOnehot 973 } 974 975 val robIdxVec = entries.io.robIdx.get 976 val uopIdxVec = entries.io.uopIdx.get 977 val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec) 978 979 deqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR 980 deqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt 981 finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR && deqBeforeDly.head.ready 982 finalDeqSelOHVec.head := deqSelOHVec.head 983 984 for (i <- entries.io.enq.indices) { 985 entries.io.enq(i).bits.status match { case enqData => 986 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 987 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 988 989 // update blocked 990 val isLsqHead = { 991 s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get && 992 s0_enqBits(i).sqIdx <= memIO.sqDeqPtr.get 993 } 994 enqData.blocked := !isLsqHead 995 } 996 } 997 998 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 999 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1000 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1001 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1002 slowResp.bits.fuType := DontCare 1003 slowResp.bits.uopIdx.get := 0.U // Todo 1004 } 1005 1006 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1007 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1008 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1009 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1010 fastResp.bits.fuType := DontCare 1011 fastResp.bits.uopIdx.get := 0.U // Todo 1012 } 1013 1014 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1015 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1016 1017 1018 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1019 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1020 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1021 if (params.isVecLduIQ) { 1022 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1023 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1024 } 1025 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1026 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1027 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1028 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1029 } 1030} 1031